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[Other resource] abel-hdl DL : 0: lattice的abel-hel开发文档，对cpld开发的朋友会有用-the lattice-CAS documentation, the development of cpld be friends with
Update : 2008-10-13 Size : 645.23kb Publisher : evan
[Windows Develop] abel DL : 0: abela beier 编程-program with abela beier
Update : 2025-02-17 Size : 4kb Publisher : 许的虎
[Other Embeded program] dataio DL : 0: GAL开发工具，abel语言编译器-GAL development tools, compiler abel
Update : 2025-02-17 Size : 517kb Publisher : 孟松
[VHDL-FPGA-Verilog] PCI_PIO DL : 0: 不足20元的PCI设计，含ABEL源代码。-PCI design less than 20Yuan ,including ABEL code
Update : 2025-02-17 Size : 180kb Publisher : kata
[VHDL-FPGA-Verilog] abel-hdl DL : 0: lattice的abel-hel开发文档，对cpld开发的朋友会有用-the lattice-CAS documentation, the development of cpld be friends with
Update : 2025-02-17 Size : 645kb Publisher : evan
[Other Embeded program] ABEL4.RAR DL : 0: ABEL语言的编译器，在DOS下使用。内有READ.TXT文件，使用前请看之。-ABEL language compiler, the use of DOS. There READ.TXT documents, please see it before use.
Update : 2025-02-17 Size : 914kb Publisher : 张平
[GPS develop] labeltool-1 DL : 0: abel Tool Sample Requires: Visual Basic 6 and MapObjects 2.x Data: redlands.shp (Redlands sample data set from MO 2.x) Interactive Labeling Tool If the check box is checked, then the mouse down location will search for the closest line, and label it with the street name. If the check box is not checked, then the mouse down will turn into a pan/zoom tool. There is a slider bar to control the search tolerance in screen pixels for the labeling. -abel Tool Sample Requires: Visual Basic 6 and MapObjects 2.x Data: redlands.shp (Redlands sample data set from MO 2.x) Interactive Labeling Tool If the check box is checked, then the mouse down location will search for the closest line, and label it with the street name. If the check box is not checked, then the mouse down will turn into a pan/zoom tool. There is a slider bar to control the search tolerance in screen pixels for the labeling.
Update : 2025-02-17 Size : 185kb Publisher : tnth2so4
[Embeded-SCM Develop] PLDprogrammingnote DL : 0: PLD编程笔记使用abel语言的有关个人心得笔记-PLD programming language abel use of the personal experiences Notes
Update : 2025-02-17 Size : 154kb Publisher : fsdf
[Books] ispDesignExpert DL : 0: 第一节 ispDesignEXPERT 简介第二节 ispDesignEXPERT System 的原理图输入第三节设计的编译与仿真第四节 ABEL 语言和原理图混合输入第五节 ispDesignEXPERT System 中 VHDL 和Verilog 语言的设计方法第六节在系统编程的操作方法第七节 ModelSim 的使用方法附录一 ispDesignEXPERT System 上机实习题附录二 ispDesignEXPERT System 文件后缀及其含义-Introduction Section II, section I ispDesignEXPERT ispDesignEXPE RT System III schematic design input to the compilation and simulation fourth ABEL language and schematics mixed input System V ispDesignEXPERT VHDL and Verilog language the statement in section VI Design System Programming methods of operation of the sect ModelSim use is an appendix pDesignEXPERT System attachment that the plane Appendix 2 ispDesignEXPE RT System file extension and its meaning
Update : 2025-02-17 Size : 1.23mb Publisher : 吴忌
[Other Embeded program] 16V8 DL : 0: 这是用AHDL语言即abel语言编写的逻辑可编程器件原代码！供大家参考！-This is AHDL is abel language programmable logic devices original code! For your reference!
Update : 2025-02-17 Size : 129kb Publisher : 帅冲
[Other] 8695321 DL : 0: abel语言的相当优秀实例多媒体教程！这个在网上很少见的。-abel language quite outstanding examples of multimedia tutorial! The online rare.
Update : 2025-02-17 Size : 277kb Publisher : 帅冲
[Other] ABEL_REF DL : 0: ABEL 语言参考书详细介绍了ABEL的语法是HDL硬件设计的初级语言. 对HDL硬件设计人员仍然有用.-ABEL language reference books detail the ABEL syntax HDL hardware design is the primary language. Right HDL hardware designers still useful.
Update : 2025-02-17 Size : 797kb Publisher : 谢云松
[Other] In-systemProgrammableSolutions1 DL : 0: 目录第一节ispDesignEXPERT 简介第二节ispDesignEXPERT System 的原理图输入第三节设计的编译与仿真第四节ABEL 语言和原理图混合输入第五节ispDesignEXPERT System 中 VHDL 和Verilog 语言的设计方法第六节在系统编程的操作方法第七节ModelSim 的使用方法附录一ispDesignEXPERT System 上机实习题附录二ispDesignEXPERT System 文件后缀及其含义-Contents Section I Introduction Section II ispDesignEXPERT the ispDesignEXPERT System schematic design input Section III Section IV ABEL compiler and simulation language and schematic diagram in section V ispDesignEXPERT System hybrid input in VHDL and Verilog design language of section VI in the system programming method of operation to use the ModelSim section VII of Appendix 1 ispDesignEXPERT System-on internship title ispDesignEXPERT System Appendix II document and the meaning of the suffix
Update : 2025-02-17 Size : 519kb Publisher : 史蒙克
[Other] ABEL DL : 0: 简要说明：本系统是基于DOS版本的ABEL4的基础上写的一个windows界面，希望能为大家使用上带来一点方便。由于本人对ABEL4的理解上还很不透彻，所以很多地方可能还是存在着错误。如果您有什么好的建议，或者处理方法上的建议，请来信指教。-err
Update : 2025-02-17 Size : 1.06mb Publisher : 郭艳杰
[SCM] solution1324 DL : 0: SX-CPLD/FPGA 数字逻辑电路设计实验仪 SX-CPLD/FPGA 数字逻辑电路设计实验仪产品介绍 1.利用CPLD/FPGA 提供的软硬件开发环境学习最新逻辑IC 设计，以取代TTL/CMOS 复杂的硬件设计。 2.可使用电路绘图法、ABEL 语言、波形图和数字硬件描述语言法(VHDL/AHDL)来开发电路。 3.CPLD/ FPGA 提供引脚可任意设定,故作测试实验时不需要做硬件连接,可节省大量连线焊接时间,快速学习软硬件的运用。 4.CPLD/ FPGA 每一I/O Pin 皆有逻辑状态监视器，以便迅速了解每一引脚状态。 5.清楚标示每一管脚的脚位，易于观察和测量。 6.使用并口在开发系统下直接下载。 7.可在线将CPLD/ FPGA 程序到FLASH ROM，实验仪可独立运行，适合大学生EDA 电子竞赛。 8.可做8051 和CPLD/ FPGA 的组合电路实验。 9.适用于WINDOWS95/98/NT/2000/XP 操作系统。 10.数万门的现场可编程芯片让设计所思即所得。 -err
Update : 2025-02-17 Size : 167kb Publisher : vobno
[ELanguage] abel DL : 0: 16V8例程,应用GEL16V8实现的振荡器,振荡频率为300k-20Hz-16V8 routines, application GEL16V8 realize the oscillator, oscillation frequency for the 300k-20Hz
Update : 2025-02-17 Size : 89kb Publisher : 王宇野
[Software Engineering] abel DL : 0: ABEL PLD 可编程逻辑元件参考语法-ABEL PLD
Update : 2025-02-17 Size : 154kb Publisher : axin
[Other] ABEL Primer DL : 0: ABEL HDL Primer
Update : 2025-02-17 Size : 63kb Publisher : bbg
[Other] ABEL RefMan DL : 0: ABEL HDL Reference Manual
Update : 2025-02-17 Size : 699kb Publisher : bbg
[Other] Xilinx ABEL User Guide DL : 0: ABEL HDL User Guide
Update : 2025-02-17 Size : 1.32mb Publisher : bbg

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