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[Other resource] 01_GettingStarted DL : 0: This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP Examples directory.-This exercise will guide y ou through the step-by-step process of transfo rming a MATLAB floating-point model into a hard ware module that can be implemented in silicon ( FPGA or ASIC). The design is a general purpose FI R filter taken from the AccelDSP Examples direc tory.
Update : 2008-10-13 Size : 5.36kb Publisher : 杨平
[Other resource] 03_Quantization DL : 0: This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable by using quantize directives.-This lab exercise will introduce you to Acc elDSP's floating-to fixed-point conversion f eatures. AccelDSP will automatically generat e a fixed-point representation of a floating-p oint design. This process is controllable by us ing quantize directives.
Update : 2008-10-13 Size : 26.48kb Publisher : 杨平
[Other resource] 06_DesignExploration DL : 0: This lab exercise will cover the use of AccelDSP’s design exploration capabilities that include mapping variables to memory and unrolling loop and vector operations. You will learn how to create different hardware architectures without modifying the MATLAB source to explore different area/performance tradeoffs.-This lab exercise will cover the use of Acce lDSP's design exploration capabilities that i nclude mapping variables to memory and unrolli Vi loop and vector operations. You will learn ho w to create different hardware architectures w ithout modifying the MATLAB source to explore d ifferent area / performance tradeoffs.
Update : 2008-10-13 Size : 53.05kb Publisher : 杨平
[Other resource] 07_AddingHardwareControl DL : 0: Often it is necessary to add some logical control to a MATLAB algorithm to allow the generated hardware to function correctly in the overall system. This lab exercise will explore how hardware control can be added to a MATLAB algorithm and synthesized using AccelDSP Synthesis.-Often it is necessary to add some logical co ntrol to a MATLAB algorithm to allow the generat ed hardware to function correctly in the overal l system. This lab exercise will explore how har dware control can be added to a MATLAB algorithm and synthesized using AccelDSP Synthesis.
Update : 2008-10-13 Size : 51.75kb Publisher : 杨平
[Other resource] AccelDSP DL : 0: AccelDSP Synthesis Tool Floating-Point to Fixed-Point Conversion of MATLAB Algorithms Targeting FPGAs
Update : 2008-10-13 Size : 293.41kb Publisher : hesonwhb
[Other Embeded program] 01_GettingStarted DL : 0: This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP Examples directory.-This exercise will guide y ou through the step-by-step process of transfo rming a MATLAB floating-point model into a hard ware module that can be implemented in silicon ( FPGA or ASIC). The design is a general purpose FI R filter taken from the AccelDSP Examples direc tory.
Update : 2025-02-17 Size : 5kb Publisher : 杨平
[Other Embeded program] 03_Quantization DL : 0: This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable by using quantize directives.-This lab exercise will introduce you to Acc elDSP's floating-to fixed-point conversion f eatures. AccelDSP will automatically generat e a fixed-point representation of a floating-p oint design. This process is controllable by us ing quantize directives.
Update : 2025-02-17 Size : 26kb Publisher : 杨平
[Other Embeded program] 06_DesignExploration DL : 0: This lab exercise will cover the use of AccelDSP’s design exploration capabilities that include mapping variables to memory and unrolling loop and vector operations. You will learn how to create different hardware architectures without modifying the MATLAB source to explore different area/performance tradeoffs.-This lab exercise will cover the use of Acce lDSP's design exploration capabilities that i nclude mapping variables to memory and unrolli Vi loop and vector operations. You will learn ho w to create different hardware architectures w ithout modifying the MATLAB source to explore d ifferent area/performance tradeoffs.
Update : 2025-02-17 Size : 53kb Publisher : 杨平
[Other Embeded program] 07_AddingHardwareControl DL : 0: Often it is necessary to add some logical control to a MATLAB algorithm to allow the generated hardware to function correctly in the overall system. This lab exercise will explore how hardware control can be added to a MATLAB algorithm and synthesized using AccelDSP Synthesis.-Often it is necessary to add some logical co ntrol to a MATLAB algorithm to allow the generat ed hardware to function correctly in the overal l system. This lab exercise will explore how har dware control can be added to a MATLAB algorithm and synthesized using AccelDSP Synthesis.
Update : 2025-02-17 Size : 51kb Publisher : 杨平
[Software Engineering] AccelDSP DL : 0: AccelDSP Synthesis Tool Floating-Point to Fixed-Point Conversion of MATLAB Algorithms Targeting FPGAs
Update : 2025-02-17 Size : 293kb Publisher : hesonwhb
[DSP program] dds_001 DL : 0: 基于Matlab和AccelDSP开发工具设计的一个数字频率综合器实例（DDS）。可以参考学习如何使用AccelDSP。-AccelDSP development tools based on Matlab and the design of an instance of a digital frequency synthesizer (DDS). Can refer to learn how to use AccelDSP.
Update : 2025-02-17 Size : 6kb Publisher : lyd
[VHDL-FPGA-Verilog] accledsp DL : 0: xilinx accel dsp实例项目工程-xilinx accel dsp project
Update : 2025-02-17 Size : 21kb Publisher : ocean
[Other] FIR DL : 0: 这是一个在MATLAB上编写的FIR滤波器程序，并能被AccelDSP综合，下载到Xilinx上进行硬件仿真，适合对AccleDSP学习的人应用-This is a MATLAB program to write the FIR filter, and can be integrated AccelDSP downloaded to the Xilinx on hardware simulation, suitable for application on AccleDSP learn,
Update : 2025-02-17 Size : 860kb Publisher : qiwen
[matlab] Edgetect DL : 0: Update : 2025-02-17 Size : 18kb Publisher : taoufik
[Data structs] kibgklk8 DL : 0: This lab exercise will cover the use of AccelDSP’s design ex,-This lab exercise will cover the use of AccelDSP s design ex,
Update : 2025-02-17 Size : 25kb Publisher : xyndmi
[Algorithm] 054943 DL : 0: This lab exercise will cover the use of AccelDSP’s design ex,-This lab exercise will cover the use of AccelDSP s design ex,
Update : 2025-02-17 Size : 53kb Publisher : Afnrey
[Data structs] rxbexerkise DL : 0: This lab exercise will introduce you to AccelDSP’s floating-,-This lab exercise will introduce you to AccelDSP s floating -
Update : 2025-02-17 Size : 26kb Publisher : Afnrey
[Process-Thread] cdver DL : 0: This lab exercise will cover the use of AccelDSP’s design ex,-This lab exercise will cover the use of AccelDSP s design ex,
Update : 2025-02-17 Size : 25kb Publisher : noife
[Process-Thread] wilbAccelDSP DL : 0: This lab exercise will introduce you to AccelDSP’s floating-,-This lab exercise will introduce you to AccelDSP s floating -
Update : 2025-02-17 Size : 25kb Publisher : coapjgl
[Graph program] UhyelDSP-AccelDSP DL : 0: This lab exercise will introduce you to AccelDSP’s floating-,(This lab exercise will introduce you to AccelDSP 's floating -- -)
Update : 2025-02-17 Size : 24kb Publisher : xmriarping

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