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[VHDL-FPGA-Verilog] fifo

Description: 此程序为存储器常用的FIFO（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory FIFO (FIFO), the procedure is not specified bit, so more suitable for beginners to apply
Platform: | Size: 1024 | Author: zhaohongliang | Hits:

[VHDL-FPGA-Verilog] AD0809

Description:
Platform: | Size: 4339712 | Author: 侯训平 | Hits:

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