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[VHDL-FPGA-Verilog] ADC_16bit

Description: 用verilog硬件描述语言编写的16位数模转换器的源代码，可以综合-with verilog hardware description language of 16 Digital to Analog source code can be integrated
Platform: | Size: 1024 | Author: awp | Hits:

[Embeded-SCM Develop] verilog.HDL.examples

Description: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Platform: | Size: 188416 | Author: 张驰 | Hits:

[SCM] adc

Description: 编写verilog代码 利用实验箱上的A/D芯片完成模数转换。输入电压由实验箱提供，其幅值在0~5V间变化，由电位器控制。输出信号显示输入的模拟电压值，由数码管显示为2位BCD码的形式。-The preparation of Verilog code box on the use of experimental A/D chip to complete analog-digital conversion. Input voltage provided by the experimental box, and its amplitude in the 0 ~ 5V between changes in control by potentiometer. Output signal shows that the value of analog voltage input from a digital display for two BCD code of the form.
Platform: | Size: 22528 | Author: Ericwhu | Hits:

[Other Embeded program] ADCcaiyang

Description: 模数转换器AD976采样控制器程序Verilog实现，基于状态机实现-AD976 ADC sampling procedures Verilog realize the controller, based on the state machine to achieve
Platform: | Size: 180224 | Author: cj | Hits:

[VHDL-FPGA-Verilog] ADC

Description: 用verilog编程实现的基于FPGA的AD数据采集程序-Verilog Programming with FPGA-based data collection procedures AD
Platform: | Size: 499712 | Author: 张西贝 | Hits:

[VHDL-FPGA-Verilog] adc_verilog

Description: adc verilog 用verilog编写的sigma-delta adc例子 应用在计量类adc产品-adc verilog Verilog prepared using sigma-delta adc examples used in the measurement adc Product category
Platform: | Size: 3072 | Author: 张鸿 | Hits:

[VHDL-FPGA-Verilog] ADControl

Description: 此程序为Verilog控制ADC的全部程序，已检验可以应用-This procedure for the Verilog control ADC all procedures can be applied to test
Platform: | Size: 140288 | Author: Johonson | Hits:

[VHDL-FPGA-Verilog] ADCtest

Description: 利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the
Platform: | Size: 589824 | Author: ticklay | Hits:

[VHDL-FPGA-Verilog] ADC_INTERFACE

Description: it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
Platform: | Size: 6144 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] ADC_CONTROL_VERYLOG

Description: 运行在FPGA上的Verilog程序(实现对ADC的控制)-Verilog procedures (the achievement of the control of the ADC)
Platform: | Size: 320512 | Author: lion | Hits:

[VHDL-FPGA-Verilog] ADC

Description: verilog code for ADC
Platform: | Size: 1024 | Author: nhat | Hits:

[VHDL-FPGA-Verilog] ADControl

Description: 用verilog实现，ADC控制，源代码，可进行仿真-Verilog with the realization of, ADC control, source code, can be simulated
Platform: | Size: 139264 | Author: 代鑫 | Hits:

[Other] verilog-A_library

Description: Complete Verilog-A library for analog blocks, like ADC, DAC, amplifiers
Platform: | Size: 80896 | Author: zhanglh | Hits:

[VHDL-FPGA-Verilog] Verilog_ADCtestcode

Description: ADC测试的verilog代码，可以下载到FPGA上面实现对ADC性能测试。-the test code for ADC of verilog
Platform: | Size: 145408 | Author: 刘晓志 | Hits:

[VHDL-FPGA-Verilog] adc_spi

Description: dsp通过SPI接口数据采集 sigma-delta ADC采集程序-dsp through the SPI interface, data acquisition sigma-delta ADC acquisition program
Platform: | Size: 8192 | Author: xingtian | Hits:

[VHDL-FPGA-Verilog] AD0819

Description: 利用verilog语言实现对AD0819的模数转换控制，源代码工程文件-Verilog language used on the AD0819' s ADC control, source code project files
Platform: | Size: 98304 | Author: lifejoy | Hits:

[VHDL-FPGA-Verilog] 16bitADC

Description: verilog实现的16位模数转换器参考源代码-verilog to achieve 16-bit ADC reference source code
Platform: | Size: 1024 | Author: 龚俊杰 | Hits:

[VHDL-FPGA-Verilog] ADC

Description: a verilog code about dac of audio codec on fpga board.
Platform: | Size: 1024 | Author: DCLAB | Hits:

[VHDL-FPGA-Verilog] adc

Description: 设计ADC控制器，Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器，采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
Platform: | Size: 3072 | Author: 钟雪美 | Hits:

[Program doc] berckley pipeline adc verilog model

Description: berckley pipeline adc verilog model
Platform: | Size: 1457664 | Author: beidawuxi123 | Hits:
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