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[Documents] ripple-lookahead-carryselect-adder DL : 0: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Update : 2025-02-17 Size : 15kb Publisher : 李成
[VHDL-FPGA-Verilog] ADDER DL : 0: 经过精心设计的加法器的代码，并在FPGA硬件平台实现和验证过的-Meticulously designed adder code, and FPGA hardware platform and tested
Update : 2025-02-17 Size : 1kb Publisher : hewg
[VHDL-FPGA-Verilog] VHDL-ADDER DL : 0: VHDL的N位加法器，非常的好用，经过仿真验证的！-VHDL N-bit adder, very easy to use, after the simulation!
Update : 2025-02-17 Size : 1kb Publisher : 郭荣天
[VHDL-FPGA-Verilog] adder DL : 0: 高达16位加法器的实现，工作环境在ISE，modesim，该例程较为详细！-Up to 16-bit adder implementation, the working environment at ISE, modesim, the more detailed routines!
Update : 2025-02-17 Size : 50kb Publisher : 马高望
[VHDL-FPGA-Verilog] adder DL : 0: 加法器可做4BIT的運算用直接語言撰寫-Adder computing can 4BIT
Update : 2025-02-17 Size : 306kb Publisher : 劉家亦
[VHDL-FPGA-Verilog] adder DL : 0: 采用加法树流水线乘法构造八位乘法器，并分析设计的性能和结果在时钟节拍上落后的影响因素。 -Multiplication using adder tree structure line 8 multiplier, the design and analysis of the results of the performance and beat the clock on the impact of the factors behind.
Update : 2025-02-17 Size : 1.18mb Publisher : 张炳良
[VHDL-FPGA-Verilog] adder DL : 0: verilog 加法器设计在modelsim下方针-verilog adder
Update : 2025-02-17 Size : 1015kb Publisher : 兰书明
[MiddleWare] ADDER DL : 0: 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
Update : 2025-02-17 Size : 272kb Publisher : 王强
[VHDL-FPGA-Verilog] ADDER DL : 0: simple 16-bit CSA Adder
Update : 2025-02-17 Size : 64kb Publisher : calvin
[VHDL-FPGA-Verilog] adder DL : 0: 一位全加器可由两个一位半加器与一个或门构成，该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路-A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical description method, first of all the design half-adder circuit, be packaged as a half-adder module and then call at the top half-adder composed of full-adder circuit modules
Update : 2025-02-17 Size : 154kb Publisher : 哈哈
[MPI] Parallel-adder DL : 0: 并行加法器是一种数位电路，其可进行数字的加法计算。在现代的电脑中，加法器存在于算术逻辑单元（ALU）之中。加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。-Parallel adder is a digital circuit, which can be calculated the number of addition. In the modern computer, adder exists in the arithmetic logic unit (ALU) into. Adder can be used to express a variety of values, such as: BCD, plus three yards, the major is based on a binary adder for computing.
Update : 2025-02-17 Size : 3kb Publisher : jlz
[Other] adder DL : 0: 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
Update : 2025-02-17 Size : 38kb Publisher : zhaozimou
[VHDL-FPGA-Verilog] Floating-Point-Adder DL : 0: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Update : 2025-02-17 Size : 151kb Publisher : 凌音
[VHDL-FPGA-Verilog] floating-point-adder DL : 0: verilog implementation of the floating point adder
Update : 2025-02-17 Size : 2kb Publisher : ramtin
[VHDL-FPGA-Verilog] VHDL-ripple-lookahead-carryselect-adder DL : 0: vhdl code for ripple carry adder, carry select adder and carry look ahead adder
Update : 2025-02-17 Size : 17kb Publisher : praveen
[VHDL-FPGA-Verilog] 32-rip-adder DL : 0: A ripple carry adder allows you to add two 32-bit numbers
Update : 2025-02-17 Size : 1kb Publisher : kaream
[Embeded-SCM Develop] 16-bit-adder DL : 0: 这是关于16位加法器的实现代码及仿真图形的压缩文档-This is about 16-bit adder implementation code and simulation graphics archive
Update : 2025-02-17 Size : 173kb Publisher : 王重
[Software Engineering] A-New-Reversible-Design-of-BCD-Adder DL : 0: Designing a BCD adder
Update : 2025-02-17 Size : 102kb Publisher : Anand
[VHDL-FPGA-Verilog] Optimized-design-of-BCD-adder-and-Carry DL : 0: Optimized design of BCD adder and Carry
Update : 2025-02-17 Size : 170kb Publisher : Christoffer
[VHDL-FPGA-Verilog] Adder and Counter VHDL DL : 0: Source code of a full adder and a counter VHDL.
Update : 2017-04-15 Size : 178byte Publisher : hameye

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