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[Crack Hack] AES算法

Description: 一个非常好的ASE代码，通过实验证明能编译通过-A perfect AES program code, and it can be run after translation and edition.
Platform: | Size: 209920 | Author: 张力 | Hits:

[Crack Hack] aes_core

Description: AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
Platform: | Size: 79872 | Author: | Hits:

[Crack Hack] mini_aes

Description: aes算法的verilog hdl实现，供给大家作为参考 。-Orangk'aes algorithm verilog hdl realized, we supply as a reference.
Platform: | Size: 240640 | Author: 杨忠宇 | Hits:

[Crack Hack] aes_core

Description: Verilog实现AES加密算法 密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用-AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied
Platform: | Size: 79872 | Author: yuansuchun | Hits:

[VHDL-FPGA-Verilog] aes_core.tar

Description: AES的Verilog实现,用于加密的算法硬件实现!-AES realize the Verilog for hardware implementation of encryption algorithms!
Platform: | Size: 69632 | Author: 刘志刚 | Hits:

[Crack Hack] verilog

Description: 用于aes128加密的扩展密钥算法，比较详细-For the expansion of key aes128 encryption algorithm, a more detailed
Platform: | Size: 11264 | Author: zsh | Hits:

[VHDL-FPGA-Verilog] AES_RTL

Description: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Platform: | Size: 15360 | Author: 林夢魔 | Hits:

[Crack Hack] AES

Description: AES算法的verilog代码，即AES算法IP核-ip core for AES
Platform: | Size: 13312 | Author: JJ | Hits:

[source in ebook] 63535312DCTofJPEG

Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Platform: | Size: 2048 | Author: jiang | Hits:

[Crack Hack] aes_crypto_core_latest.tar

Description: verilog code for aes
Platform: | Size: 1927168 | Author: vani | Hits:

[Crack Hack] aes_thesis_v1.0

Description: AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
Platform: | Size: 386048 | Author: 蕭嵎之 | Hits:

[Crack Hack] aes

Description: 其程序是用xilinx环境下编写的，风格是Verilog，请大家提意见。-The program is written using xilinx environment, style Verilog, please comments.
Platform: | Size: 3072 | Author: 郝志刚 | Hits:

[VHDL-FPGA-Verilog] aes

Description: verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
Platform: | Size: 7168 | Author: xie | Hits:

[VHDL-FPGA-Verilog] aes-core

Description: Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
Platform: | Size: 88064 | Author: fujiwei | Hits:

[Crack Hack] aes-verilog-imp

Description: AES加密算法的硬件实现，硬件语言为verilog-AES encryption algorithm hardware implementation, hardware verilog language
Platform: | Size: 6144 | Author: 程家诺 | Hits:

[VHDL-FPGA-Verilog] verilog-files

Description: Verilog implementation of AES
Platform: | Size: 23552 | Author: suba | Hits:

[Crack Hack] aes

Description: AES in verilog codes
Platform: | Size: 28672 | Author: Ni Ni | Hits:

[Crack Hack] AES-GF(2^4)^2 for sbox

Description: AES加解密程序，128bit数据位宽，其中sbox和混合列运算在复合域GF(2^4)^2上完成(An AES encryption and decryption program with 128 bits datawidth, which used GF(2^4)^2 for sbox and mixcolumn.)
Platform: | Size: 17408 | Author: 酱瓶 | Hits:

[VHDL-FPGA-Verilog] aes

Description: AES FPGA verilogHDL实现(AES hardware implementation)
Platform: | Size: 36864 | Author: 猪在飞 | Hits:

[Crack Hack] aes-master

Description: Verilog写的AES加密解密代码，带testbench。(AES encryption code written by Verilog with testbench.)
Platform: | Size: 69632 | Author: 容止 | Hits:
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