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Description: AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
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Size: 540672 |
Author: Bill Guan |
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Description: AHB总线协议 Master实现代码,对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
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Size: 1024 |
Author: 龙的传人 |
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Description: this project relates ahb
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Size: 268288 |
Author: david |
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Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
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Size: 17408 |
Author: jinjin |
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Description: 关于千兆以太网的硕士论文,一边的mac层,一边是ahb总线slave接口。写的非常好。-Master s thesis on Gigabit Ethernet, while the mac layer, one side is ahb bus slave interface. Write very well.
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Size: 1324032 |
Author: einstein |
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Description: Advanced High speed bus protocol
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Size: 434176 |
Author: Shanthan |
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Description: ahb总线代码,现支持4个master,可扩展-ahb bus verilog module
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Size: 28672 |
Author: ross |
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Description: AHB BUS, Master Slave Arbiter,AHB System是由Master,Slave,Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
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Size: 537600 |
Author: zcvip1 |
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Description: AHB总线接口描述,MASTER的接口描述,AMB总线协议(AHB bus interface description, MASTER interface description, AMB bus protocol)
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Size: 4096 |
Author: 小萌子
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Description: verilog实现AHB总线上的主从控制,在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
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Size: 36864 |
Author: 落叶无情1992
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