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[Other resource] leon3-altera-ep2s60-sdr

Description: ahb sdram interface.arm cpu series,include controller
Platform: | Size: 98080 | Author: lhxmodelsim | Hits:

[MiddleWare] leon3-altera-ep2s60-sdr

Description: ahb sdram interface.arm cpu series,include controller
Platform: | Size: 98304 | Author: | Hits:

[Other] appnote65_quickmips_ahb_interface_design_example.r

Description: appnote65_quickmips_ahb_interface_design_example AHB接口设计-appnote65_quickmips_ahb_interface_design_exampleAHB Interface Design
Platform: | Size: 542720 | Author: Bill Guan | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] CAST_sdr_sdram_ctrl-xact

Description: Single Data Rate Mobile SDRAM Controller Core with AHB Interface
Platform: | Size: 733184 | Author: gosha | Hits:

[VHDL-FPGA-Verilog] AHB_SRRAM

Description: SSRAM with AHB bus interface source code
Platform: | Size: 205824 | Author: nan | Hits:

[VHDL-FPGA-Verilog] eth

Description: 一个ahb接口的千兆以太网MAC，包括apb的配置接口-Ahb a Gigabit Ethernet interface MAC, including the configuration interface apb
Platform: | Size: 31744 | Author: daisy | Hits:

[VHDL-FPGA-Verilog] ahb_ram

Description: AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such means of transmission), other means of transmission is no problem
Platform: | Size: 1024 | Author: Jasking Wu | Hits:

[VHDL-FPGA-Verilog] slaveAHB

Description: amba总线的AHB部分，与从机相连接口的写法，载自其它网页。-amba AHB bus parts from the machine connected to the interface with the wording set out from other pages.
Platform: | Size: 2048 | Author: yang sally | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM

Description: 基于ARM核的嵌入式CPU内AHB接口的实现。-CPU based on ARM core embedded within the AHB interface.
Platform: | Size: 82944 | Author: 陈锴 | Hits:

[VHDL-FPGA-Verilog] USB2_0

Description: USB2_0设备控制器IP核的AHB接口技术。-USB2_0 Device Controller IP Core AHB interface technology.
Platform: | Size: 288768 | Author: 陈锴 | Hits:

[VHDL-FPGA-Verilog] AHB-Default-Slave-Module

Description: AMBA2.0版本AHB总线缺省从设备设计方面的技术支持，参考ARM公司AMBA技术手册。对AHB缺省从设备电路的接口、基本逻辑等方面进行介绍。-AMBA2.0 version of the default from the AHB bus support equipment design, ARM AMBA technology reference manual. Default on the AHB slave interface circuit, the basic logic, etc. are introduced.
Platform: | Size: 73728 | Author: 杨宗凯 | Hits:

[VHDL-FPGA-Verilog] AHB-Decoder-Module

Description: AMBA2.0版本AHB总线译码单元设计方面的技术支持，参考ARM公司AMBA技术手册。对AHB译码单元电路的接口、基本逻辑等方面进行介绍。-AMBA2.0 version of the AHB bus decoding unit design technical support, refer to ARM AMBA technical manual. AHB decoder unit circuit of the interface, basic logic, etc. are introduced.
Platform: | Size: 90112 | Author: 杨宗凯 | Hits:

[VHDL-FPGA-Verilog] ahb_verilog_design

Description: 代码为ahb interface ，用verilog编写的,包括仿真和综合。-Code for the interface AHB, written in Verilog, including simulation and synthesis.
Platform: | Size: 538624 | Author: 陈奇 | Hits:

[VHDL-FPGA-Verilog] ahb_ebc

Description: Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
Platform: | Size: 10240 | Author: scnn86 | Hits:

[VHDL-FPGA-Verilog] Ahb2Apb

Description: AHB总线协议转APB总线协议的接口IP，使用Verilog代码实现，有详细的英文注释(AHB bus protocol turn APB bus interface IP, use Verilog code implementation, and have a detailed knowledge of the English comments)
Platform: | Size: 5120 | Author: local_boy | Hits:

[VHDL-FPGA-Verilog] ahb_master

Description: AHB总线接口描述，MASTER的接口描述，AMB总线协议(AHB bus interface description, MASTER interface description, AMB bus protocol)
Platform: | Size: 4096 | Author: 小萌子 | Hits:

[Other] AHB RAM

Description: Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Platform: | Size: 21811200 | Author: 容止 | Hits:

[VHDL-FPGA-Verilog] ahb_task

Description: ahb接口的sram做读写测试的读写时序(SRAM of the AHB interface for reading and writing tests)
Platform: | Size: 287744 | Author: pt呀呀呀 | Hits:

[VHDL-FPGA-Verilog] dma_ahb_latest.tar

Description: AHB DMA verilog源码 AHB总线 DMA接口源码(AHB bus DMA interface source code)
Platform: | Size: 661504 | Author: 翾飞FEI | Hits:
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