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Description: ahb sdram interface.arm cpu series,include controller
Platform: |
Size: 98080 |
Author: lhxmodelsim |
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Description: ahb sdram interface.arm cpu series,include controller
Platform: |
Size: 98304 |
Author: |
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Description: 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度就可以了.-FPGA has been successfully controlled by SDRAM controller code. As long as you need to modify the width of it.
Platform: |
Size: 187392 |
Author: chen qiming |
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Description: Single Data Rate Mobile SDRAM Controller Core
with AHB Interface
Platform: |
Size: 733184 |
Author: gosha |
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Description: 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is OSCI SystemC 2.2.0. All of the hardware modules satisfies the OSCI standards.
The simulator is composed of a CPU, cache, and memory components including DDR SDRAM, MLC NOR Flash, MLC NAND Flash, SRAM. Each memory components have it’s own memory model, which enables cycle-accurate power consumption estimation of the devices. Master and slave SystemC IPs are connected through AMBA AHB CLI (Cycle-Level Interface). You will get energy trace files for each memory devices. You will get cycle-accurate performance evaluation results CPU cycle counts information, and cache hit/miss ratio on console. Also, you can get trace files for memory devices.
The simulator exhibits performance over 500 K instructions/sec, which is fairly high for a cycle-accurate system-level simulator.
The simulator’s source co
Platform: |
Size: 4886528 |
Author: Archie |
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Description: 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
Platform: |
Size: 209920 |
Author: guoxiaojin |
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