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[Other resource] SLAVERAM

Description: AHB slave 的一个简单的原型程序，通过参考该程序，可以写出相应的ahb slave 代码
Platform: | Size: 1736 | Author: goodboy2716 | Hits:

[Other] ahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
Platform: | Size: 269312 | Author: 木石 | Hits:

[VHDL-FPGA-Verilog] SLAVERAM

Description: AHB slave 的一个简单的原型程序，通过参考该程序，可以写出相应的ahb slave 代码-AHB slave prototype of a simple procedure, by referring to the program, you can write the corresponding code ahb slave
Platform: | Size: 1024 | Author: goodboy2716 | Hits:

[Other] ahb_interface

Description: AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
Platform: | Size: 540672 | Author: Bill Guan | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] CODE

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram verilog
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[Software Engineering] ram_top

Description: arm ahb slave bus sram ip in verilog
Platform: | Size: 2048 | Author: msd | Hits:

[VHDL-FPGA-Verilog] generic_ahb_slave

Description: Generic AHB Slave for all AHB slave transactions
Platform: | Size: 1024 | Author: Vbhat | Hits:

[VHDL-FPGA-Verilog] AN123

Description: AMBA Application Note: AN123 - Logic Tile IT1 GPIO example design. -Application note AN123 provides all of the AHB slave features of AN119 with the addition of five 32bit AHB GPIO slaves. The GPIO interfaces are used to configure and test an IT1 board. The following board combinations are supported: Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1 Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1 Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1 Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1 PB926EJ-S+ LT-XC2V6000+ IT1 PB926EJ-S+ LT-XC2V8000+ IT1 Asynchronous and Synchronous bridge modes are supported on the PB926EJ-S with different design images. Asynchronous mode is selected using SW1[3] on the PB926EJ-S.
Platform: | Size: 4482048 | Author: 余曉民 | Hits:

[VHDL-FPGA-Verilog] ahb_slave_latest.tar

Description: this shows the ip code for amba ahb slave in vhdl.
Platform: | Size: 5120 | Author: sachin | Hits:

[VHDL-FPGA-Verilog] AHB-BUS-AND-SLAVE-CODE-USING-VERILOG

Description: AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
Platform: | Size: 34816 | Author: xuqinjiang | Hits:

[VHDL-FPGA-Verilog] AHB_slave-ram

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
Platform: | Size: 1024 | Author: 吴亮 | Hits:

[VHDL-FPGA-Verilog] AHB-Default-Slave-Module

Description: AMBA2.0版本AHB总线缺省从设备设计方面的技术支持，参考ARM公司AMBA技术手册。对AHB缺省从设备电路的接口、基本逻辑等方面进行介绍。-AMBA2.0 version of the default from the AHB bus support equipment design, ARM AMBA technology reference manual. Default on the AHB slave interface circuit, the basic logic, etc. are introduced.
Platform: | Size: 73728 | Author: 杨宗凯 | Hits:

[Software Engineering] AHBtoAPB

Description: AHBtoAPB设计基于AMBA总线协议的APB Bridge设计-AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.
Platform: | Size: 114688 | Author: 李雷 | Hits:

[Other] ahb_slave

Description: AHB SLave code in verilog
Platform: | Size: 12288 | Author: Especially for you! | Hits:

[VHDL-FPGA-Verilog] ahb_slave

Description: 主要是用来描述的ahb slave的文件-ahb slave file
Platform: | Size: 1024 | Author: 李伟 | Hits:

[Other] ahb_slave_latest.tar

Description: AHB slave its code snippets and spec file explanations. You can find slave code which you can develop a code for slave in a better way.-AHB slave its code snippets and spec file explanations. You can find slave code which you can develop a code for slave in a better way.
Platform: | Size: 5120 | Author: Vicky | Hits:

[VHDL-FPGA-Verilog] ahb

Description: verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
Platform: | Size: 36864 | Author: 落叶无情1992 | Hits:

[Other] AHB2-master

Description: verilog ahb master and slave
Platform: | Size: 31744 | Author: chandu1212 | Hits:

[VHDL-FPGA-Verilog] AHB-task-slave-master

Description: ahb master行为级模型，ahb slave模型(AHB master behavior level model, AHB slave model)
Platform: | Size: 2048 | Author: 鱼在在藻 | Hits:
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