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Description: 开源的基于SystemC的模拟器,可以模拟ARM CPU, Cache, DDR,NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is OSCI SystemC 2.2.0. All of the hardware modules satisfies the OSCI standards.
The simulator is composed of a CPU, cache, and memory components including DDR SDRAM, MLC NOR Flash, MLC NAND Flash, SRAM. Each memory components have it’s own memory model, which enables cycle-accurate power consumption estimation of the devices. Master and slave SystemC IPs are connected through AMBA AHB CLI (Cycle-Level Interface). You will get energy trace files for each memory devices. You will get cycle-accurate performance evaluation results CPU cycle counts information, and cache hit/miss ratio on console. Also, you can get trace files for memory devices.
The simulator exhibits performance over 500 K instructions/sec, which is fairly high for a cycle-accurate system-level simulator.
The simulator’s source co
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Size: 4886528 |
Author: Archie |
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Description: arm ahb slave bus sram ip in verilog
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Size: 2048 |
Author: msd |
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Description: amba ahb to sram verilog
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Size: 2048 |
Author: namkin |
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Description: Verilog写的 AHB总线接口的SRAM代码,带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
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Size: 21811200 |
Author: 容止 |
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Description: amba总线的ahb到sram的接口,Verilog代码,还算详细,算是不错的资料。(The AHB to SRAM interface of the AMBA bus)
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Size: 329728 |
Author: zzf仗剑天涯 |
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Description: ahb接口的sram做读写测试的读写时序(SRAM of the AHB interface for reading and writing tests)
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Size: 287744 |
Author: pt呀呀呀 |
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Description: 基于AHB总线的sram控制器,带有memory bist(SRAM controller based on AHB bus)
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Size: 3254272 |
Author: 重新注册 |
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Description: 一款verilog设计的SRAM控制器,可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)
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Size: 3379200 |
Author: fkmeng |
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Description: AHS-SRAM的实践项目讲解和PPT介绍(Introduction to Practical Projects of AHS-SRAM and PPT)
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Size: 1517568 |
Author: aspirin |
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