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[VHDL-FPGA-Verilog] AMBAcode(vhdl)

Description: vhdl实现的amba代码-realize the AMBA VHDL code
Platform: | Size: 201728 | Author: sk | Hits:

[Other] ahb_interface

Description: AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
Platform: | Size: 540672 | Author: Bill Guan | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] tb_ahb_master

Description: this is a AMBA AHB code for master.
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] New

Description: amba ahb master decoder
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] amba

Description: AMBA VHDL源代码.讲解的很详细，看看有什么可以借鉴的地方。-AMBA VHDL sourse
Platform: | Size: 35840 | Author: wusheer | Hits:

[ARM-PowerPC-ColdFire-MIPS] apb_bridge

Description: arm ambm 2.0 primecell算法 ahb 与 apb通讯的转换模块-arm ambm 2.0 primecell algorithm ahb conversion and communications module apb
Platform: | Size: 2048 | Author: sunk | Hits:

[VHDL-FPGA-Verilog] CAST_sdr_sdram_ctrl-xact

Description: Single Data Rate Mobile SDRAM Controller Core with AHB Interface
Platform: | Size: 733184 | Author: gosha | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA_V2.0_CN

Description: ARM公司高级微控制器总线体系（Advanced Microcontroller Bus Architecture AMBA ）规范中文版，包括ASB，AHB，APB总线-Senior ARM microcontroller bus system (Advanced Microcontroller Bus Architecture AMBA) specification, including the ASB, AHB, APB bus
Platform: | Size: 1077248 | Author: 陶戈丹 | Hits:

[VHDL-FPGA-Verilog] masterdecoder

Description: AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[MiddleWare] slaveAHB

Description: 基于ahb协议写的简单salve，水平有限莫怪啊-Ahb-based protocol to write a simple salve, is limited No wonder, then ah
Platform: | Size: 2048 | Author: 将为会 | Hits:

[VHDL-FPGA-Verilog] apb2ahb

Description: verilog code for apb to ahb convert
Platform: | Size: 1024 | Author: peng | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
Platform: | Size: 198656 | Author: guoxiaojin | Hits:

[VHDL-FPGA-Verilog] eth

Description: 一个ahb接口的千兆以太网MAC，包括apb的配置接口-Ahb a Gigabit Ethernet interface MAC, including the configuration interface apb
Platform: | Size: 31744 | Author: daisy | Hits:

[VHDL-FPGA-Verilog] AHBtoAPB

Description: amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc-amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
Platform: | Size: 165888 | Author: zhangyiyun | Hits:

[VHDL-FPGA-Verilog] ahb_ram

Description: AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such means of transmission), other means of transmission is no problem
Platform: | Size: 1024 | Author: Jasking Wu | Hits:

[VHDL-FPGA-Verilog] arm9verilog

Description: AMBA AHB verilog Source code
Platform: | Size: 195584 | Author: Frank Chen | Hits:

[Software Engineering] MAC-IP

Description: 关于千兆以太网的硕士论文，一边的mac层，一边是ahb总线slave接口。写的非常好。-Master s thesis on Gigabit Ethernet, while the mac layer, one side is ahb bus slave interface. Write very well.
Platform: | Size: 1324032 | Author: einstein | Hits:

[VHDL-FPGA-Verilog] ahb_mas.tar

Description: its shows the ip of amba ahb master in vhdl
Platform: | Size: 23552 | Author: sachin | Hits:

[VHDL-FPGA-Verilog] ahb_slave_latest.tar

Description: this shows the ip code for amba ahb slave in vhdl.
Platform: | Size: 5120 | Author: sachin | Hits:
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