Location:
Search - altera D
Search list
Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制,将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A / D chip to control the collection, image data are stored in synchronous FIFO - AL422B
Platform: |
Size: 1151 |
Author: 古韦剑 |
Hits:
Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制,将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A/D chip to control the collection, image data are stored in synchronous FIFO- AL422B
Platform: |
Size: 1024 |
Author: 古韦剑 |
Hits:
Description: 数字预失真在通信领域内IP核的开发文档,包括数学表达式及硬件框图-Digital Predistortion in the field of IP communications in the development of nuclear documents, including mathematical expression and hardware block diagram
Platform: |
Size: 1397760 |
Author: 聂华 |
Hits:
Description: 8051 MCU在nois平台上实现的说明文档,讲解非常详细,对于设计很有帮助,出自Altera公司。-nois 8051 MCU platform in the realization of documentation to explain in great detail, useful for the design, from Altera Corporation.
Platform: |
Size: 134144 |
Author: 钟方 |
Hits:
Description: altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。-altera
Platform: |
Size: 15360 |
Author: 朱峰 |
Hits:
Description: FPGA+DA转换,ALTERA公司FPGA与DA实现,DA转换功能!-FPGA+ DA conversion, ALTERA company FPGA and DA realize, DA conversion!
Platform: |
Size: 16384 |
Author: 19820521 |
Hits:
Description: 用EPM7032(CPLD)做的2路8位并行输入DAC,带内部环型振荡器(不用外接时钟振荡源)。-With EPM7032 (CPLD) to do 2-way 8-bit parallel input DAC, with the internal ring oscillator (no external clock oscillation source).
Platform: |
Size: 3072 |
Author: 邵刚 |
Hits:
Description: This an exercise in using finite state machines.基于ALTERA的DE2开发
平台,设计一个有限状态机FSM(finite state machines).-This an exercise in using finite state machines. Based on ALTERA s DE2 development platform to design a finite state machine FSM (finite state machines).
Platform: |
Size: 75776 |
Author: sopc |
Hits:
Description: Altera de2 开发板的使用指南,论述了DE2开发板所有配套实例的使用方法-Altera de2 development board
Platform: |
Size: 2759680 |
Author: 陈建 |
Hits:
Description: DMA调试经验,NIOS II环境下,适用altera公司芯片-DMA debugging experience, NIOS II environment, the application of altera-chip companies
Platform: |
Size: 1024 |
Author: yeyoushi |
Hits:
Description: altera 飓风二代开发板的原理图,pdf格式
-altera hurricane of the second generation development board schematics, pdf format
Platform: |
Size: 236544 |
Author: dansen |
Hits:
Description: Altera Modesim破解版的LICENCE.
下载解压后:
1.直接运行mentorkg.exe(生成的license.txt拷贝到D:\altera\80\modelsim_ae\下或者mentorkg.exe拷贝到此目录下运行).
2.设置环境变量lm_license_file="D:\altera\80\modelsim_ae\license.txt"
3.搞定-Altera Modesim cracked version of the LICENCE. Decompress after download: 1. Direct running mentorkg.exe (generated copy license.txt to the D: altera80modelsim_ae the next copy of this directory or mentorkg.exe run) .2. Lm_license_file = Set environment variables D: altera80modelsim_aelicense.txt 3. get
Platform: |
Size: 313344 |
Author: xingyu |
Hits:
Description: Pacman 4 DE1-FPGA-Board
Platform: |
Size: 943104 |
Author: bert1970 |
Hits:
Description: 基于ALTERA公司的NIOSII的串口通信DMA传输设计-NIOSII based on ALTERA s DMA transfer of the serial communication design
Platform: |
Size: 11346944 |
Author: 王超 |
Hits:
Description: quartus多种USB-bletera 自制下载线!
Platform: |
Size: 2328576 |
Author: 陈长佳 |
Hits:
Description: tlv5614的驱动程序,用verilog语言编写的,fpga芯片为altera公司的ep2c35。
调试成功放心使用-tlv5614 driver, using verilog language written in, fpga chips altera company ep2c35. Assured the success of the use of debugging
Platform: |
Size: 352256 |
Author: 王乐 |
Hits:
Description: 基于FPGA的音频信号A/D转换,适用于DE2开发板。-FPGA-based audio signal A/D conversion, for DE2 development board.
Platform: |
Size: 34816 |
Author: wendy |
Hits:
Description: altera DE1 用户手册各种功能描述以及管脚分配-altera DE1 User Manual
Platform: |
Size: 2126848 |
Author: jiang |
Hits:
Description: Altera公司的基于NIOSII设计DDR和DDR2内存的资料,很有帮助的,-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
Platform: |
Size: 3154944 |
Author: iyoung |
Hits:
Description: design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.-design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.
Platform: |
Size: 1024 |
Author: weichenghao |
Hits: