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[VHDL-FPGA-VerilogAudio_DAC_FIFO

Description: altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。-altera
Platform: | Size: 15360 | Author: 朱峰 | Hits:

[VHDL-FPGA-Verilogaltera_fifo

Description: altera 公司的 FIFO 文档,这是设计同步或异步FIFO的重要文档-altera s FIFO document
Platform: | Size: 294912 | Author: liuminghua | Hits:

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