Search - altera image

[assembly language] saa7111_2

Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A / D chip to control the collection, image data are stored in synchronous FIFO - AL422B
Platform: | Size: 1151 | Author: 古韦剑 | Hits:

[Special Effects] Video_and_mage_Processing

Description: The example design provides a framework for rapid development of video and image processing designs using the library of parameterizable MegaCore® functions available in the Altera Video and Image Processing Suite.
Platform: | Size: 1208938 | Author: 普林斯 | Hits:

[assembly language] saa7111_2

Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A/D chip to control the collection, image data are stored in synchronous FIFO- AL422B
Platform: | Size: 1024 | Author: 古韦剑 | Hits:

[Documents] DE2_scheamtics

Description: Altera 公司的DE2板子的原理图 PDF格式-Altera s DE2 board schematic diagram of the PDF format
Platform: | Size: 363520 | Author: 肖海涛 | Hits:

[Special Effects] Video_and_mage_Processing

Description: The example design provides a framework for rapid development of video and image processing designs using the library of parameterizable MegaCore® functions available in the Altera Video and Image Processing Suite.
Platform: | Size: 1208320 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] CPLD_Config

Description: 用Altera CPLD做为控制器从Flash上读取image文件对Altera FPGA编程-Altera CPLD used as a controller to read image from the Flash on the Altera FPGA programming
Platform: | Size: 4096 | Author: jwq | Hits:

[Special Effects] auto_graphics_ref_design-v1.0.4

Description: 基于NIONII的图像获取与真彩屏LCD显示例子，非常好。通过修改可适用于ALTERA的FPGA多个系列。-Based on the image acquisition NIONII color LCD display with real examples, very good. By modifying the applicable ALTERA multiple series of FPGA.
Platform: | Size: 20955136 | Author: zhanghh624 | Hits:

[VHDL-FPGA-Verilog] 61EDA

Description: 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案，针对视频解码芯片 ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII 系列FPGA(EP2C35)上实现。结果显示本设计具有速度高、成本低、易于集成等优点-Analysis of a variety of video capture programs reviewed. On how to use CCD camera capture high-resolution, high-quality images, as well as FPGA-based embedded video image acquisition system realization method was studied. Used to camera mode+ decoder chip collection program for video decoder chip ADV7181B, realized the I2C bus configuration, ITU656 decoder, VGA display module design. The video capture controller has been designed in the Altera' s CycloneII series FPGA (EP2C35) to achieve. The results showed that this design has a high speed, low cost, easy to integrate the advantages of
Platform: | Size: 179200 | Author: 李明 | Hits:

[Video Capture] DE2_70_schematic_v11

Description: altera基于ep2c70的图像采集处理平台设计方案。完整的设计原理图。-altera-based image acquisition and processing platform ep2c70 design. Complete design schematic.
Platform: | Size: 514048 | Author: ami | Hits:

[VHDL-FPGA-Verilog] ug_vip

Description: Altera公司原版设计手册，关于video and image processing ip-This document describes the Altera® Video and Image Processing Suite collection of IP cores that ease the development of video and image processing designs. You can use the following IP cores in a wide variety of image processing and display applications.
Platform: | Size: 1402880 | Author: Han Yunbo | Hits:

[VHDL-FPGA-Verilog] CORDIC_FPGA

Description: 摘要：本文在传统CORDIC算法的基础之上，通过增加迭代次数，对参数进行了优化筛选，提高了运算精度，使设计出的软核能够在精度要求较高的场合中运行，如实时语音、图像信号处理、滤波技术等。输出数据经过IEEE-754标准化处理，能够直接兼容大多数处理器，扩展了其应用范围。最终在Altera公司NiosⅡ处理器中通过增加自定义指令的方式完成了硬件实现。关键字：CORDIC ,自定义指令, IEEE-754标准化处理。-Abstract: In this paper, based on the traditional CORDIC algorithm, by increasing the number of iterations, selection of parameters were optimized to improve the computing precision, the design of the soft-core to the occasion in the high precision in the running, such as real-time voice , image signal processing, filtering technology. IEEE-754 output data after standardization, can be directly compatible with most processors, expanded its scope of application. Altera, Nios Ⅱ ultimately by the processor the way to add custom instructions to complete the hardware. Keywords: CORDIC, custom instruction, IEEE-754 standard treatment.
Platform: | Size: 228352 | Author: daisywmc | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案，针对视频解码芯片 ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII 系列FPGA(EP2C35)上实现。结果显示本设计具有速度高、成本低、易于集成等优点-Analysis of a variety of video capture programs reviewed. On how to use CCD camera capture high-resolution, high-quality images, as well as FPGA-based embedded video image acquisition system realization method was studied. Used to camera mode+ decoder chip collection program for video decoder chip ADV7181B, realized the I2C bus configuration, ITU656 decoder, VGA display module design. The video capture controller has been designed in the Altera s CycloneII series FPGA (EP2C35) to achieve. The results showed that this design has a high speed, low cost, easy to integrate the advantages of
Platform: | Size: 4064256 | Author: looksky | Hits:

[VHDL-FPGA-Verilog] fpga-display-bmp-pictures

Description: 本文设计的是基于大规模FPGA的BMP图库管理，完成了数码相框的一部分功能。并且本文详细地介绍了BMP图库管理的软硬件实现，即采用Altera的CyclonII系列EP2C20F484C7作为主控芯片，内嵌32位的NiosII软核，采用SDRAM作为内存，把存储在SD卡内的二进制图片信息读入内存，并控制TFT彩色液晶，读取图片数据送到液晶上显示。整个过程的所有设备都是通过Avalon总线挂在NiosII上，在NiosII的协调下正常工作。本作品最终能显示存入SD卡内的彩色图片信息，图片显示很流畅，没有延时。并且能通过4个按键分别完成图片的上翻、下翻、放大和缩小。-This design is based on the large-scale FPGA-BMP library management, and completed part of the features of digital photo frame. This paper describes the library management software and hardware to achieve BMP photos, that used the Altera s CyclonII series EP2C20F484C7 as the master chip, embedded soft-core 32-bit NiosII, the use of SDRAM for memory, SD card stored the binary picture information read into memory, and control TFT color LCD, read the image form the memory data to the LCD display. All equipment of the process hanging in the NiosII through Avalon bus, with the NiosII CPU and complete the coordination of work. Eventually the work can show the color pictures of information stored into the SD card, pictures show smoothly, and with no delay. And with 4 keys, respectively, we can make the TFT display the previous image or the next image,and make the pictures zoom in or zoom out.
Platform: | Size: 2168832 | Author: wuwei | Hits:

[VHDL-FPGA-Verilog] DE1_fat32

Description: 本文设计的是基于大规模FPGA的BMP图库管理，完成了数码相框的一部分功能。并且本文详细地介绍了BMP图库管理的软硬件实现，即采用Altera的CyclonII系列EP2C20F484C7作为主控芯片，内嵌32位的NiosII软核，采用SDRAM作为内存，把存储在SD卡内的二进制图片信息读入内存，并控制TFT彩色液晶，读取图片数据送到液晶上显示。整个过程的所有设备都是通过Avalon总线挂在NiosII上，在NiosII的协调下正常工作。本作品最终能显示存入SD卡内的彩色图片信息，图片显示很流畅，没有延时。并且能通过4个按键分别完成图片的上翻、下翻、放大和缩小。-This design is based on the large-scale FPGA-BMP library management, and completed part of the features of digital photo frame. This paper describes the library management software and hardware to achieve BMP photos, that used the Altera s CyclonII series EP2C20F484C7 as the master chip, embedded soft-core 32-bit NiosII, the use of SDRAM for memory, SD card stored the binary picture information read into memory, and control TFT color LCD, read the image form the memory data to the LCD display. All equipment of the process hanging in the NiosII through Avalon bus, with the NiosII CPU and complete the coordination of work. Eventually the work can show the color pictures of information stored into the SD card, pictures show smoothly, and with no delay. And with 4 keys, respectively, we can make the TFT display the previous image or the next image,and make the pictures zoom in or zoom out.
Platform: | Size: 11721728 | Author: wuwei | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_CCD_detect_b

Description: 本程序基于Altera公司的DE2平台完成仓库的实时监控并对移动的目标进行自动识别和报警的FPGA设计，研究重点就是图像采集和移动目标识别的FPGA实现。采用Altera公司的DC2模版对视频进行采集并将采集到的图像信息进行缓存，通过监视器实时显示，采用帧间差分法对采集到的帧图像进行运动检测，当仓库中有运动情况的时候，两个图像间灰度会出现异常，通过对灰度异常的侦测完成仓库移动目标的识别并蜂鸣器报警。-Complete real-time monitoring of the warehouse and moving target based on the Altera DE2 platform FPGA design of automatic identification and alarm, the research focus of the image acquisition and recognition of the moving target FPGA implementation. Altera Corporation DC2 template image acquisition and acquisition information to cache the video monitor real-time display, inter-frame difference method for motion detection frames collected, when the movement in the warehouse. between the gray scale in the two images will be abnormal, the warehouse moving target identification grayscale exception detection and buzzer alarm.
Platform: | Size: 19487744 | Author: wangyi | Hits:

[Windows Develop] aDE2_70_scheml

Description: altera基于ep2c70的图像采采集处理平台设计方案。完整的设计原理图。 -The altera based image ep2c70 mining acquisition and processing platform design. Complete design schematic.
Platform: | Size: 514048 | Author: nicollejia | Hits:

[Windows Develop] A61EDAn

Description: 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案，针对视频频解码芯片ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII系列FPGA(EP2C35)上实现。结果显 -Status of a variety of video capture programs. How to use the CCD camera to capture high-resolution, high-quality images, as well as FPGA-based embedded video image acquisition system has been studied. Decoder chip to the camera+ acquisition program, the configuration of the I2C bus for the video frequency decoding chip ADV7181B ITU656 decoding VGA display module design. The design of the video capture controller Altera Corporation CycloneII series FPGA (EP2C35). Results significantly
Platform: | Size: 180224 | Author: noahkk | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[assembly language] saa7111_2

[Special Effects] Video_and_mage_Processing

[assembly language] saa7111_2

[Documents] DE2_scheamtics

[Special Effects] Video_and_mage_Processing

[VHDL-FPGA-Verilog] CPLD_Config

[Special Effects] auto_graphics_ref_design-v1.0.4

[VHDL-FPGA-Verilog] 61EDA

[Video Capture] DE2_70_schematic_v11

[VHDL-FPGA-Verilog] ug_vip

[VHDL-FPGA-Verilog] CORDIC_FPGA

[VHDL-FPGA-Verilog] DE2_TV

[VHDL-FPGA-Verilog] fpga-display-bmp-pictures

[VHDL-FPGA-Verilog] DE1_fat32

[VHDL-FPGA-Verilog] DE2_LCM_CCD_detect_b

[Windows Develop] aDE2_70_scheml

[Windows Develop] A61EDAn

[Special Effects] image-processing

[VHDL-FPGA-Verilog] Video-and-Image-Processing-Suite

[VHDL-FPGA-Verilog] CCD_Array

CodeBus www.codebus.net