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[Other resource] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114780 | Author: king.xia | Hits:

[Books] modelsim使用教程

Description: 一本不错的介绍modemsim的电子书，希望能给大家带来些帮助-a good introductory modemsim of e-books, in hopes of giving us some more help
Platform: | Size: 342016 | Author: 周玲玲 | Hits:

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114688 | Author: | Hits:

[VHDL-FPGA-Verilog] EP2C20_ALTERA_3462031

Description: altera的器件手册，型号为ep2c20，希望对大家有用-altera device manuals, models ep2c20, everyone wishes to be useful
Platform: | Size: 2621440 | Author: st.filo | Hits:

[Other] altera_modelsim

Description: 比较详细的总结，个人花了一天写的，很好的哟-A more detailed summary, individuals spent a day writing, good yo
Platform: | Size: 1274880 | Author: 刘国华 | Hits:

[VHDL-FPGA-Verilog] music

Description: 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频系数的分频，产生符合某一音乐的频率，然后再引入4HZ的时钟为音乐的节拍控制，最后通过扬声器放出来。 -Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
Platform: | Size: 8192 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] altera_modelsim

Description: modelsim6.0—altera 详细的教程，肯定能教会你，比网上那些好多了，分享给大家-good！
Platform: | Size: 1274880 | Author: 陈海涛 | Hits:

[VHDL-FPGA-Verilog] EP3C25

Description: altera公司的EP3C25的官方参考设计，对开发类似型号的产品设计有很大帮助-EP3C25 altera' s official reference design, product design and development of similar models of great help
Platform: | Size: 70656 | Author: 王钊 | Hits:

[Software Engineering] xilinx_altera

Description: XILINX 与 ALTERA 两家FPGA的比较,其中涉及了资源\速度\型号\性能等,比较时编译软件都采取了较多设置,可以保证正确性.-XILINX and ALTERA FPGA comparison of two, which involves a resource \ speed \ models \ performance, etc., when compared to compiled software have taken more settings, you can guarantee correctness.
Platform: | Size: 22528 | Author: 刘成岩 | Hits:

[VHDL-FPGA-Verilog] fft_32k

Description: FFT 32K点设计实例v1.0.0自述文件 本自述文件包含以下部分： 工具要求 o Quartus II编译 o ModelSim仿真模型 o MATLAB模型(FFT 32K Point Design Example v1.0.0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design example posted on the Altera Support website: http://www.altera.com/support/examples/exm-index.html Ensure that you have read the information on the design example web page before using the example. This readme file contains the following sections: o Package Contents o Tool Requirements o Quartus II Compilation o ModelSim Simulation Models o MATLAB Models o Core Directory Names o Release History o Design Examples Disclaimer o Contacting Altera)
Platform: | Size: 1120256 | Author: wsf-jv | Hits:

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