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[Other resource] sdr sdram controller DL : 0: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Update : 2008-10-13 Size : 2.35mb Publisher : 陈东平
[SourceCode] altera sdram controller DL : 1: altera sdram controller vhdl
Update : 2011-03-17 Size : 2.26mb Publisher : langzhongfeilang@126.com
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] sdr sdram controller DL : 0: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Update : 2025-02-17 Size : 2.34mb Publisher : 陈东平
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2025-02-17 Size : 427kb Publisher : kevin
[Other] AlteraSDRAMControllerWhitePaper DL : 0: Altera SDRAM Controller 白皮书，很详细的文档-Altera SDRAM Controller White Paper, a very detailed document
Update : 2025-02-17 Size : 685kb Publisher : wood
[MiddleWare] leon3-altera-ep2s60-sdr DL : 0: ahb sdram interface.arm cpu series,include controller
Update : 2025-02-17 Size : 96kb Publisher :
[Embeded-SCM Develop] SDRAM DL : 0: SDRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board
Update : 2025-02-17 Size : 1.5mb Publisher : 李大同
[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Update : 2025-02-17 Size : 112kb Publisher :
[Compress-Decompress algrithms] rd1010_source_code DL : 0: 使用FPGA做SDRAM控制器 -SDRAM controller using FPGA so
Update : 2025-02-17 Size : 349kb Publisher :
[Software Engineering] sdrsdramuse DL : 0: 一篇讲解ALTERA的FPGA如何实现SDR SRAM的指导文章。很有指导意义。-ALTERA s FPGA on a how to achieve the guidance of SDR SRAM articles. Great guiding significance.
Update : 2025-02-17 Size : 685kb Publisher : kurt
[VHDL-FPGA-Verilog] H1wQqGvI DL : 0: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL-Described in detail ALTERA device IP CORE and how to use SDR SDRAM CONTROL
Update : 2025-02-17 Size : 759kb Publisher : 黄辉辉
[ARM-PowerPC-ColdFire-MIPS] SDRAM DL : 0: ALTERA SDR AM Controller White Paper
Update : 2025-02-17 Size : 643kb Publisher : 付茗
[VHDL-FPGA-Verilog] source DL : 1: SDRAM通用接口程序，和Altera所给标准一致-SDRAM generic interface procedures, and to the standards by Altera
Update : 2025-02-17 Size : 14kb Publisher : 王并
[VHDL-FPGA-Verilog] sdram DL : 0: sdram test controller altera -sdram test controller altera
Update : 2025-02-17 Size : 1.45mb Publisher : yangchun
[SCM] DE2_70_User_manual_v101 DL : 0: Altera DE2-70开发板的使用手册-Altera DE2-70 development board manual
Update : 2025-02-17 Size : 3.51mb Publisher : 桑圣锋
[VHDL-FPGA-Verilog] AlteraSdramIP DL : 0: Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written
Update : 2025-02-17 Size : 763kb Publisher : 张敏
[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog DL : 0: 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Update : 2025-02-17 Size : 758kb Publisher : 费尔德
[VHDL-FPGA-Verilog] AlteraSDR-SDRAM DL : 0: Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
Update : 2025-02-17 Size : 792kb Publisher : machenghai
[VHDL-FPGA-Verilog] AlteraSdramIP DL : 0: Altera Sdram IP 源码.rar-Altera Sdram IP source code. Rar
Update : 2025-02-17 Size : 707kb Publisher : hu71992

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