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Description: Splitter file to be used to split altera avalon st video stream into two avalon st streams.
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Size: 237568 |
Author: formjk |
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Description: design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.
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Size: 1398784 |
Author: ak |
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Description: rs32 stream fpga beard altera
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Size: 1219584 |
Author: zouggari boualem |
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Description: 由于altera公司的CRC生成和校验模块不支持本系统使用的Cyclone IV E系列FPGA，因此本文独立设计了CRC模块。该模块的接口与altera公司的CRC模块接口基本一致，能够对16位输入的数据流进行CRC校验码生成和校验。本文采用CRC-CCITT生成项，其表达式为：X16+X12+X5+X0。本模块需要startp信号及endp信号指示数据传输的起始及结束。本模块采用状态机设计，对于数据头和数据尾分别由不同的状态来处理。在本模块中，使用了for循环，这会消耗较多的FPGA资源，但暂时任未发现其他改进的方法。-Because altera company' s CRC generation and checking modules do not support the use of the system Cyclone IV E series FPGA, so this independent design of the CRC module. The module' s interface with the CRC module interface altera' s basically the same, capable of 16-bit input data stream of CRC generation and checking. In this paper, CRC-CCITT generation entry, its expression is: X16+ X12+ X5+ X0. This module requires startp signal and endp signal indicating the start and end of data transmission. This module is a state machine design, and data for the end of the first data were handled by different states. In this module, use the for loop, which consumes more FPGA resources, but temporarily did not find any other ways to improve.
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Size: 4096 |
Author: 陈建 |
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Description: The Altera® Video Over IP Reference Design implements a system that
bridges between MPEG transport stream (TS) data and Ethernet-based
internet protocol (IP) networks.-The Altera® Video Over IP Reference Design implements a system that
bridges between MPEG transport stream (TS) data and Ethernet-based
internet protocol (IP) networks.
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Size: 500736 |
Author: gaob |
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Description: 在altera的FPGA上实现直接数字频率合成，即用verilog实现DDS，输出正弦波形，在modelsim软件中仿真通过，已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim software, already contains all the code and engineering as well as binary stream file.
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Size: 694272 |
Author: 汪少锋 |
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Description: 介绍altera的video over ip的参考设计-The Altera ® Video Over IP Reference Design implements a system that
bridges between MPEG transport stream (TS) data and Ethernet-based
internet protocol (IP) networks.
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Size: 516096 |
Author: hife |
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Description: Altera 关于VIP使用的详细说明，对于理解VIP有很好的帮助，是一个很好的资料。-The Altera® Video and Image Processing Design Example demonstrates the following
items:
■ A framework for rapid development of video and image processing systems
■ Dynamic scaling, clipping, flashing, moving, sharpening and FIR filtering of both
standard definition (SD) and high definition (HD) inputs
■ Picture-in-picture mixing with a background layer
■ Run-time control of different parts of the system, including a radar that uses onscreen display functions.
■ Debugging components for monitoring the video stream within the datapath
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Size: 758784 |
Author: shen xiaoyu |
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Description: AES3在altera FPGA上开发的参考案例-AES3 Reference Design v1.0
The AES3/EBU reference design provides both a transmitter and a
receiver. The receiver extracts the data and the clock an incoming
AES3/EBU stream and stores the parallel audio data and control bits into
a FIFO buffer.
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Size: 4664320 |
Author: 刘星 |
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