Search - alu 16 bit

[VHDL-FPGA-Verilog] verilog实现ALU的源代码

Description: verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
Platform: | Size: 1024 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
Platform: | Size: 2048 | Author: 李斌 | Hits:

[VHDL-FPGA-Verilog] MyCPU16

Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 1089536 | Author: 孙冰 | Hits:

Description: 三种16位整数运算器的ALU设计方法，调用库函数74181（4位ALU），组成串行16位运算器。(用74181的正逻辑) B．调用库函数74181和74182，组成提前进位16位运算器。(用74181的正逻辑) 注意：调74181库设计，加进位是“0”有效，减借位是“1”有效，所以最高位进位或借位标志寄存器要统一调整到高有效 C．用always @，case方式描述16位运算器。-Three 16-bit integer arithmetic logic unit of the ALU design methodology, called library function 74181 (4 ALU), composed of serial 16-bit arithmetic logic unit. (With 74,181 positive logic) B. Call library functions 74181 and 74182 to form the advance into the 16-bit arithmetic logic unit. (With 74,181 positive logic) Note: 74,181 Treasury tune the design, add bit is
Platform: | Size: 1024 | Author: yifang | Hits:

[Com Port] Alu1232

Description: An 8-bit ALU with 16 operations: logic, arithmetic, shifts.
Platform: | Size: 1024 | Author: nik | Hits:

[Windows Develop] cpu16

Description: 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic unit (ALU), memory read and write (MEM) and Write Back (WB).
Platform: | Size: 6144 | Author: 周健 | Hits:

[VHDL-FPGA-Verilog] Alu_Solution

Description: Solution for 16bit ALU component in vhdl.
Platform: | Size: 1024 | Author: andrewnick | Hits:

[VHDL-FPGA-Verilog] 16bitalu

Description: 16 bit alu using the vhdl it has 16 function perform by control unit with 4 control signal
Platform: | Size: 1002496 | Author: jai | Hits:

[VHDL-FPGA-Verilog] vhdl_for_16

Description: vhdl code for 16-bit ALU
Platform: | Size: 14336 | Author: vinoth | Hits:

[VHDL-FPGA-Verilog] vhdl-cpu-16-bit

Description: VHDL processsor 32 bit ALU SRF BUS DATA ADRESS C16 System On Chip Architecture
Platform: | Size: 976896 | Author: luis | Hits:

[VHDL-FPGA-Verilog] alu-10-10

Description: 16位运算器，包含+、-、与或非、移位等功能，内部指定a、b、cin，输入clk与rst，输出16位y与c\z标志位-16-bit arithmetic unit, including+,-, and or, shift and other functions, within the specified a, b, cin, input clk and rst, 16-bit output y and c \ z flag
Platform: | Size: 2048 | Author: 张海洋 | Hits:

[VHDL-FPGA-Verilog] MIPS-Parts

Description: // * Data Memory and IO: This is the data memory, and some IO hardware // * 8x16 register file: eight 16-bit registers // * 16-bit ALU // * 2:1 16-bit Multiplexer // * Sign extender from 7 to 16 bits // * 4:1 16-bit Multiplexer-// * Data Memory and IO: This is the data memory, and some IO hardware // * 8x16 register file: eight 16-bit registers // * 16-bit ALU // * 2:1 16-bit Multiplexer // * Sign extender from 7 to 16 bits // * 4:1 16-bit Multiplexer
Platform: | Size: 2048 | Author: Billy Bob | Hits:

[VHDL-FPGA-Verilog] myboothmul

Description: 三种16位整数运算器的ALU设计方法，调用库函数74181（4位ALU），组成串行16位运算器。(用74181的正逻辑) B．调用库函数74181和74182，组成提前进位16位运算器。(用74181的正逻辑) 注意：调74181库设计，加进位是“0”有效，减借位是“1”有效，所以最高位进位或借位标志寄存器要统一调整到高有效 C．用always @，case方式描述16位运算器-Three 16-bit integer arithmetic logic unit of the ALU design methodology, called library function 74181 (4 ALU), composed of serial 16-bit arithmetic logic unit. (With 74,181 positive logic) B. Call library functions 74181 and 74182 to form the advance into the 16-bit arithmetic logic unit. (With 74,181 positive logic) Note: 74,181 Treasury tune the design, add bit is
Platform: | Size: 177152 | Author: 王川 | Hits:

[VHDL-FPGA-Verilog] CPU-with-VHDL-16-32

Description: 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU and other modules
Platform: | Size: 1651712 | Author: | Hits:

[Software Engineering] ALU16bit

Description: design ALU 16 bit in VHDL
Platform: | Size: 349184 | Author: vinh | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 8-bit unsigned, 16 operations(arithmetic and logic).
Platform: | Size: 1024 | Author: Taffy | Hits:

[Other Embeded program] 16-bit-alu

Description: arithmetic and logic unit of sixteen bit
Platform: | Size: 10240 | Author: nadanarani | Hits:

[Algorithm] 16bit-ALU

Description: 16位ALU。包括超前进位加减法器、大小比较、算术逻辑位移等运算-16-bit ALU. Including lookahead adder-subtractor, size comparison, arithmetic and logic operations displacement
Platform: | Size: 1024 | Author: Fan | Hits:

[VHDL-FPGA-Verilog] alu

Description: 16位微处理器，能完成算数移位，逻辑移位，数字比较，逻辑运算等功能-16-bit microprocessor, to complete arithmetic shift, logical shift, numeric comparison, logical operations and other functions
Platform: | Size: 2048 | Author: Jeff | Hits:

[GIS program] alu

Description: 实现了四位快速加法器，并在此基础上实现了16位和32为快速加法器(Based on the implementation of four bit fast adder, 16 bit and 32-bit fast adders are realized)
Platform: | Size: 35840 | Author: 啊谬 | Hits:

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[VHDL-FPGA-Verilog] verilog实现ALU的源代码

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] MyCPU16

[VHDL-FPGA-Verilog] alu_16

[Com Port] Alu1232

[Windows Develop] cpu16

[VHDL-FPGA-Verilog] Alu_Solution

[VHDL-FPGA-Verilog] 16bitalu

[VHDL-FPGA-Verilog] vhdl_for_16

[VHDL-FPGA-Verilog] vhdl-cpu-16-bit

[VHDL-FPGA-Verilog] alu-10-10

[VHDL-FPGA-Verilog] MIPS-Parts

[VHDL-FPGA-Verilog] myboothmul

[VHDL-FPGA-Verilog] CPU-with-VHDL-16-32

[Software Engineering] ALU16bit

[VHDL-FPGA-Verilog] ALU

[Other Embeded program] 16-bit-alu

[Algorithm] 16bit-ALU

[VHDL-FPGA-Verilog] alu

[GIS program] alu

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