Description: 16位cpu设计VHDL源码,其中包括alu,clock,memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design Platform: |
Size: 1089536 |
Author:孙冰 |
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Description: This contains VHDL source code for a simple arithmetic logic unit. the input and results are displayed on a 4 digit 7 segment display. The user controls the input throug the use of switches. This design was created for the nexys 2 fpga but can be easily ported to other fpga s. Platform: |
Size: 8192 |
Author:hatsjoe |
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