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[VHDL-FPGA-Verilog] Arbiter

Description: Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: | Size: 2048 | Author: 夏虫 | Hits:

[VHDL-FPGA-Verilog] adma.tar

Description: 基于AMBA规范的总线VERILOG HDL 源代码-Based on the AMBA bus specification VERILOG HDL source code
Platform: | Size: 12288 | Author: maliang | Hits:

[VHDL-FPGA-Verilog] amba_verilog

Description: IC设计相关，arm内的AMBA桥实现的源码，verilog语言实现，-IC design, arm within the realization of the source AMBA bridge, verilog language,
Platform: | Size: 18432 | Author: 伊路发 | Hits:

[Other] amba3core

Description: amba3 sva 完全验证的代码，有verilog的和systemverilog的-amba3 sva fully validate the code, and the Verilog and SystemVerilog
Platform: | Size: 280576 | Author: kevin | Hits:

[Other] AMBA_cn_V1[1].0

Description: AMBA总线规范_cn_V1[1].0－中文翻译-AMBA bus specification _cn_V1 [1] .0- Chinese translation
Platform: | Size: 1095680 | Author: 刘建明 | Hits:

[Other] ahb2ahb

Description: AMBA总线AHB TO AHB bridge-AMBA bus AHB TO AHB bridge
Platform: | Size: 2048 | Author: xiaoheng | Hits:

[VHDL-FPGA-Verilog] ahb_master1

Description: this is a code of AMBA AHB master protocol in verilog
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilog] New

Description: amba ahb master decoder
Platform: | Size: 1024 | Author: bhaskar | Hits:

[Windows Develop] System_Design_and_Implementation_of_AXI_Bus

Description: AMBA AXI资料，台湾硕士论文，网上收集-AMBA AXI, Taiwanese master' s thesis, on-line collection of
Platform: | Size: 1288192 | Author: kyle | Hits:

[VHDL-FPGA-Verilog] au

Description: 基于APB总线的uart控制器，包括源码和vcs脚本-UART controller based on AMBA APB
Platform: | Size: 7168 | Author: Samuel Xu | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
Platform: | Size: 198656 | Author: guoxiaojin | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
Platform: | Size: 209920 | Author: guoxiaojin | Hits:

[VHDL-FPGA-Verilog] AHBtoAPB

Description: amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc-amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
Platform: | Size: 165888 | Author: zhangyiyun | Hits:

[Documents] AMBAaxi

Description: amba with arm processor description and use
Platform: | Size: 458752 | Author: srivastavsandy | Hits:

[VHDL-FPGA-Verilog] arm9verilog

Description: AMBA AHB verilog Source code
Platform: | Size: 195584 | Author: Frank Chen | Hits:

[VHDL-FPGA-Verilog] APB

Description: It s the verilog source code for AMBA APB 2.0 Slave
Platform: | Size: 4096 | Author: nachi | Hits:

[VHDL-FPGA-Verilog] handshake

Description: AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
Platform: | Size: 196608 | Author: nodeity | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] a_vhdl_8253_timer_latest.tar

Description: 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
Platform: | Size: 107520 | Author: 蔡搏 | Hits:

[VHDL-FPGA-Verilog] Axi_mux

Description: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Platform: | Size: 41984 | Author: Paul Stephen | Hits:
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