Welcome![Sign In][Sign Up]
Location:
Search - anand

Search list

[Other resourceAnand

Description: 用于Anand模型的数值计算的C++类,可以根据输入的参数计算出Anand模型应力应变规律-Anand model for the numerical simulation of C - can be imported under the parameters calculated Anand model of stress and strain law
Platform: | Size: 51692 | Author: 任平生 | Hits:

[AlgorithmAnand

Description: 用于Anand模型的数值计算的C++类,可以根据输入的参数计算出Anand模型应力应变规律-Anand model for the numerical simulation of C- can be imported under the parameters calculated Anand model of stress and strain law
Platform: | Size: 51200 | Author: 任平生 | Hits:

[Proxy Serverabstract.anand

Description: source detail and abstract.
Platform: | Size: 13312 | Author: aani | Hits:

[VHDL-FPGA-VerilogjkandTflipflop

Description: this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. -this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Platform: | Size: 82944 | Author: jatab | Hits:

[VHDL-FPGA-Verilogencoderdecoder

Description: this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 142336 | Author: jatab | Hits:

[VHDL-FPGA-Verilogmultiplexersemultiplexer

Description: this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 91136 | Author: jatab | Hits:

[VHDL-FPGA-VerilogsrandDflipflop

Description: this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 205824 | Author: jatab | Hits:

[VHDL-FPGA-Verilogaddersandsubtractors

Description: this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Platform: | Size: 65536 | Author: jatab | Hits:

[VHDL-FPGA-Verilogbinarytograyandgraytobinarycodeconverter

Description: this project is based on 4bit binary to gray and gray to binary code converter using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on 4bit binary to gray and gray to binary code converter using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Platform: | Size: 61440 | Author: jatab | Hits:

[matlabTrack-red-object

Description: A nice and easy object tracking by A. Bhargav Anand.
Platform: | Size: 3072 | Author: joler | Hits:

[Data structsfreebook-Ullman

Description: 《Mining of Massive Datasets》,作者:Anand Rajaraman-《Mining of Massive Datasets》,作者:Anand Rajaraman.........
Platform: | Size: 1910784 | Author: 戴平平 | Hits:

[Linux-Unixs3c2440Nor-Flash-aNand-Flasf-start

Description: TQ2440 启动过程,nor 和nandflash启动-TQ2440 start nor and norflash
Platform: | Size: 61440 | Author: 于豆豆 | Hits:

[GUI Developfoxbarcode

Description: What's New? v.0.14 - Released 2011.02.19 Fixed display correctly the digit verification code Interleved 2 of 5. Thanks Vishal Anand (India)
Platform: | Size: 378823 | Author: ordos123 | Hits:

[OtherFoxBarcode_v_0_14

Description: What s New? v.0.14 - Released 2011.02.19 Fixed display correctly the digit verification code Interleved 2 of 5. Thanks Vishal Anand (India) Fixed variable names in functions Float2Int() and Int2Float() by Anatoly Mogylevets (Canada) v.0.13 - Released 2011.01.04 Enhancement in the algorithm to generate the symbology EAN/UCC/GS1-128 Fixed the choice of a font compatible with GDI+ to display warning messages -What s New? v.0.14- Released 2011.02.19 Fixed display correctly the digit verification code Interleved 2 of 5. Thanks Vishal Anand (India) Fixed variable names in functions Float2Int() and Int2Float() by Anatoly Mogylevets (Canada) v.0.13- Released 2011.01.04 Enhancement in the algorithm to generate the symbology EAN/UCC/GS1-128 Fixed the choice of a font compatible with GDI+ to display warning messages
Platform: | Size: 378880 | Author: wei | Hits:

[assembly languageusercreep

Description: ansys的anand模型本构关系的详细代码,已经调试成功-ansys detailed code anand constitutive relationship model has been successful debugging
Platform: | Size: 2048 | Author: lixiaobin | Hits:

[Special Effectsskms

Description: Semi-supervised Kernel Mean Shift Clustering Authors: Saket Anand, Sushil Mittal, Oncel Tuzel and Peter Meer-Semi-supervised Kernel Mean Shift Clustering Authors: Saket Anand, Sushil Mittal, Oncel Tuzel and Peter MeerSemi-supervised Kernel Mean Shift Clustering Authors: Saket Anand, Sushil Mittal, Oncel Tuzel and Peter Meer
Platform: | Size: 59392 | Author: 罗明奇 | Hits:

[BooksMining-of-Massive-Datasets--Book--2014---

Description: Mining of Massive Datasets Jure Leskovec Stanford Univ. Anand Rajaraman Milliway Labs Jeffrey D. Ullman Stanford Univ.
Platform: | Size: 2793472 | Author: iamonow | Hits:

[SCMAIS328DQ

Description: ais328dq驱动程序,本代码经过测试。有比较好的接口。适合嵌入式程序开发使用。-* File Name : ais328dq_driver.c * Author : MSH Application Team * Author : Abhishek Anand * Version : $Revision:$ * Date : $Date:$ * Description : AIS328DQ driver file
Platform: | Size: 8192 | Author: 何必 | Hits:

CodeBus www.codebus.net