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[Com Port] dw_apb_uart_db

Description: 新思公司的uart数据手册，编写uart驱动必备的东东了，为公司内部资料。-Synopsys company uart data sheet, the preparation of the necessary Dongdong uart driver, and internal information for the company.
Platform: | Size: 1210368 | Author: 刘煌 | Hits:

[VHDL-FPGA-Verilog] au

Description: 基于APB总线的uart控制器，包括源码和vcs脚本-UART controller based on AMBA APB
Platform: | Size: 7168 | Author: Samuel Xu | Hits:

[VHDL-FPGA-Verilog] uart_16550

Description: UART是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中，UART用来与PC进行通信，包括与监控调试器和其它器件，如EEPROM通信。-A UART that is compatible with the industry standard 16550D includes wrappers for the Wishbone and AMBA APB busses
Platform: | Size: 244736 | Author: zhaohaiting | Hits:

[Software Engineering] apb_uart

Description: 基于APB总线的UART详细设计方案和实现-APB-based detailed design and implementation of UART
Platform: | Size: 22528 | Author: 东东 | Hits:

[VHDL-FPGA-Verilog] a_vhd_16550_uart_latest.tar

Description: A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses
Platform: | Size: 119808 | Author: Andrey | Hits:

[VHDL-FPGA-Verilog] apb_uart

Description: APB to UART , Its A bridge which converts apb transaction to UART
Platform: | Size: 238592 | Author: mubarak | Hits:

[VHDL-FPGA-Verilog] a_vhd_16550_uart

Description: 串口模块，带APB接口的。挂载APB总线上可以直接利用。-UART module with APB
Platform: | Size: 130048 | Author: my name | Hits:

[Linux-Unix] snps-dw-apb-uart

Description: Common library for ADIS16XXX devices.
Platform: | Size: 2048 | Author: mzkaliu | Hits:

[VHDL-FPGA-Verilog] apb_uart

Description: 带apb接口的uart,带testbench，测试过，可以使用(The uart module with apb interface)
Platform: | Size: 3072 | Author: songchao | Hits:

[Internet-Network] apb-uart

Description: apb—uart模块，实现中断处理和异步收发数据并处理(APB - UART module, interrupting processing and asynchronous receiving and receiving data and processing)
Platform: | Size: 4096 | Author: 王大柱 | Hits:

[Other] apb_uart_sv-pulpinov1

Description: SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
Platform: | Size: 16384 | Author: 容止 | Hits:

[VHDL-FPGA-Verilog] apb_uart

Description: 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
Platform: | Size: 2048 | Author: megmand | Hits:

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