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Description: 数字视频时域处理算法及其ASIC芯片设1.rar数字视频时域处理算法及其ASIC芯片设2.rar数字视频时域处理算法及其ASIC芯片设3.rar数字视频时域处理算法及其ASIC芯片设4.rar
数字视频时域处理算法及其ASIC芯片设5.rar
数字视频时域处理算法及其ASIC芯片设6.rar-time-domain digital video processing algorithms and ASIC chip based Digital Video 1.rar time domain processing algorithms and ASIC chip located two. rar time-domain digital video processing algorithms and ASIC chip based 3. rar Digital Video time domain processing algorithms and ASIC chip located 4. rar time-domain digital video processing algorithms and ASIC chip located 5 . rar time-domain digital video processing algorithms and ASIC chip set June. rar
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Description: 数字视频时域处理算法及其ASIC芯片设1.RAR
数字视频时域处理算法及其ASIC芯片设2.RAR
数字视频时域处理算法及其ASIC芯片设3.RAR
数字视频时域处理算法及其ASIC芯片设4.RAR
数字视频时域处理算法及其ASIC芯片设5.RAR数字视频时域处理算法及其ASIC芯片设6.RAR-time-domain digital video processing algorithms and ASIC chip based Digital Video 1.RAR time domain processing algorithms and ASIC chip located two. RAR time-domain digital video processing algorithms and ASIC chip based 3. RAR Digital Video time domain processing algorithms and ASIC chip located 4. RAR time-domain digital video processing algorithms and ASIC chip located 5 . RAR time-domain digital video processing algorithms and ASIC chip set June. RAR
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Author: sdfafaf |
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Description: 数字视频时域处理算法及其ASIC芯片设1.RAR
数字视频时域处理算法及其ASIC芯片设2.RAR
数字视频时域处理算法及其ASIC芯片设3.RAR
数字视频时域处理算法及其ASIC芯片设4.RAR
数字视频时域处理算法及其ASIC芯片设5.RAR数字视频时域处理算法及其ASIC芯片设6.RAR-time-domain digital video processing algorithms and ASIC chip based Digital Video 1.RAR time domain processing algorithms and ASIC chip located two. RAR time-domain digital video processing algorithms and ASIC chip based 3. RAR Digital Video time domain processing algorithms and ASIC chip located 4. RAR time-domain digital video processing algorithms and ASIC chip located 5 . RAR time-domain digital video processing algorithms and ASIC chip set June. RAR
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Size: 160943 |
Author: sdfafaf |
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Description: ASIC-MP4V_VID—MPEG4 ASP标准理解。本文对MPEG4标准中的Advanced Simple Profile(ASP)做一个完整的说明,作者并不只是对标准进行翻译,而是根据他当初读标准时遇到的问题,给出一个更容易理解的阅读标准的途径。-binary tree Sort of several operations, including : the establishment of two binary sort tree node insert, delete nodes, the nodes you. For a novice structure of the data useful.
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Size: 288304 |
Author: 张磊 |
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Description: 上海交大asic设计ppt-Shanghai Jiaotong University HDL design ppt
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Size: 83002 |
Author: 李牧天 |
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Description: ASIC设计教程-ASIC Design Guide
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Size: 1418488 |
Author: 张雨生 |
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Description: ASIC课程讲义
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Size: 14839912 |
Author: karsentkarsent |
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Description: Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.-Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
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Size: 2290136 |
Author: testsb |
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Description: 上海交大asic设计ppt-Shanghai Jiaotong University HDL design ppt
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Size: 82944 |
Author: 李牧天 |
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Description:
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Size: 1418240 |
Author: 张雨生 |
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Description: 一个航天航空用的Sparc处理器(配美国欧洲宇航局用的R_tems嵌入式操作系统)的VHDL源代码,但不能保证版图设计ASIC成功
-the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
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Size: 1873920 |
Author: 韩红 |
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Description: 北京里工大学ASIC设计研究所的100个
VHDL程序设计例子-Beijing University Institute of ASIC design hundred examples of VHDL Design
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Size: 198656 |
Author: 韩红 |
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Description: ASIC-MP4V_VID—MPEG4 ASP标准理解。本文对MPEG4标准中的Advanced Simple Profile(ASP)做一个完整的说明,作者并不只是对标准进行翻译,而是根据他当初读标准时遇到的问题,给出一个更容易理解的阅读标准的途径。-binary tree Sort of several operations, including : the establishment of two binary sort tree node insert, delete nodes, the nodes you. For a novice structure of the data useful.
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Size: 287744 |
Author: 张磊 |
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Description: Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and
techniques used towards ASIC chip synthesis, physical synthesis, formal
verification and static timing analysis, using the Synopsys suite of tools.-Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and
techniques used towards ASIC chip synthesis, physical synthesis, formal
verification and static timing analysis, using the Synopsys suite of tools.
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Size: 2289664 |
Author: eioruqoiu |
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Description: 介绍专用集成电路设计的一本书,很有参考价值,适合高年级本科生和研究生-Introduction ASIC design a book, a good reference for senior undergraduate and postgraduate
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Size: 3448832 |
Author: lql |
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Description: ASIC完整设计实例,帮助初学者了解ASIC的设计流程-Complete ASIC design to help beginners understand the ASIC design flow
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Size: 1705984 |
Author: mars |
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Description: 使用synopsys design compiler和 prime time进行Asic开发的英文pdf-Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design.Compiler.Physical.Compiler.And.Primetime
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Size: 4078592 |
Author: rocky |
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Description: 一個完整ASIC流程的說明文件,讓你完全了解IC Design Flow-ASIC Flow Document
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Size: 1424384 |
Author: 李昆憲 |
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Description: 芯片设计综合经典书籍
design compiler
primetime-asic synthesys
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Size: 2244608 |
Author: yin zhigang |
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Description: SoC专用集成电路的验证设计,使用Verilog语言。(Verification of ASIC SoC project with Verilog HDL langauge.)
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Size: 2997248 |
Author: renminggong
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