Search - ask in vhdl

[VHDL-FPGA-Verilog] ASKDASK

Description: ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
Platform: | Size: 96256 | Author: we | Hits:

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio

Description: NIOSII,关于MP3的源代码,用SOPC+NIOSII平台开发的,可以运行,代码详细.大家放心使用,不懂可以问我.自己写的.-NIOSII, on the MP3 source code, using SOPC+ NIOSII platform, you can run the code in detail. Members can rest assured the use, you may ask, I do not know. Wrote it myself.
Platform: | Size: 1591296 | Author: 梁佳明 | Hits:

[VHDL-FPGA-Verilog] EDA_LOCK_ALL

Description: 我EDA课程设计做的用VHDL 写的智能电子密码锁，在试验箱上实验的，4位并行密码，有报警功能与自锁功能。花了我1个星期的时间，希望对你有帮助。有什么问题可以来EMAIL问我哦。-I EDA curriculum design using VHDL to write to do the smart electronic locks, in the chamber on the experiment, four parallel passwords, has alarm function and self-locking function. I spent 1 weeks time, I hope you have help. What is the problem can come EMAIL Oh I ask.
Platform: | Size: 1005568 | Author: zw9882 | Hits:

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

Description: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度，由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Platform: | Size: 208896 | Author: 何蓓 | Hits:

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[VHDL-FPGA-Verilog] ASKDASK

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio

[VHDL-FPGA-Verilog] EDA_LOCK_ALL

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

[VHDL-FPGA-Verilog] ask

[VHDL-FPGA-Verilog] ask

[VHDL-FPGA-Verilog] Verilog

[VHDL-FPGA-Verilog] tiaozhi

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] fpga

[VHDL-FPGA-Verilog] DDS(fsk-ask-psk)

[VHDL-FPGA-Verilog] ask

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