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[Other resource] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit -
Platform: | Size: 359836 | Author: 任学 | Hits:

[Other resource] asyn_FIFO

Description: 将原始的同步状态机分解为若干个能够相互通信的子状态机,提高子状态机的自循环率,进而通过异步控制子状态机,达到降低功耗的目的. 将
Platform: | Size: 119739 | Author: maochrng | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[Other] asyn_FIFO

Description: 将原始的同步状态机分解为若干个能够相互通信的子状态机,提高子状态机的自循环率,进而通过异步控制子状态机,达到降低功耗的目的. 将-Synchronization of the original state machine is broken down into a number of months to communicate with each other sub-state machine, raise the sub-state machine of the self-circulation rate, and then through the asynchronous control of sub-state machine, to reduce power consumption purposes. Will
Platform: | Size: 119808 | Author: maochrng | Hits:

[OS Develop] asyn_fifo

Description: verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
Platform: | Size: 2048 | Author: nihao | Hits:

[Software Engineering] asyn_FIFO

Description: 该文档是学习异步FIFO 的参考文档，有需要的可以参考一下。-This document is an asynchronous FIFO to study the reference documents, there is a need that can be reference.
Platform: | Size: 1093632 | Author: 何柳 | Hits:

[Other] asyn_fifo

Description: 本文通过对异步FIFO状态的研究，提出了一种能快速准确判断异步FIFO状态的方案-Based on the state of the asynchronous FIFO, a FIFO can be quickly and accurately determine the state of the program asynchronous
Platform: | Size: 1220608 | Author: harbourliu | Hits:

[VHDL-FPGA-Verilog] SRAM_controller_of_FPGA

Description: 视频处理源码，使用pdf格式输出，用的时候自解压，然后拷贝黏贴就行了。-`timescale 1ns/1ns module asyn_fifo(clk_wr,wr_en,clk_rd,rd_en,rst,din,full,empty,dout) input clk_wr,wr_en,clk_rd,rd_en,rst input[7:0] din output full,empty output[7:0] dout reg full_temp,empty_temp,full_temp1,empty_temp1 wire full,empty wire[7:0] dout reg[9:0] cnt_wr,cnt_rd,encode_cnt_wr,encode_cnt_rd wire[9:0] gray_cnt_wr,gray_cnt_rd integer i reg[9:0] encode_a,encode_b,tempa,tempb
Platform: | Size: 59392 | Author: YZX | Hits:

[VHDL-FPGA-Verilog] AsynFIFO

Description: Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
Platform: | Size: 32768 | Author: 郑宇龙 | Hits:

[VHDL-FPGA-Verilog] asyn_fifo

Description: 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by port can be divided into TPRAM, DPRAM, TPRAM read one each port, a port read-only, write-only another port, DPRAM read each one each port, each port can either be read. This article synchronous FIFO is TPRAM (two-port RAM, a read a write).
Platform: | Size: 650240 | Author: jodyql | Hits:

[VHDL-FPGA-Verilog] asyn_fifo

Description: verilog asyn_fifo,内含详细说明,同步FIFO为TPRAM-asyn_fifo include detailed instruction，Synchronous FIFO for TPRAM
Platform: | Size: 389120 | Author: 杨莉莉 | Hits:

[Embeded-SCM Develop] asyn_FIFO-

Description: A asynchronous FIFO is implemented. VHDL fil+ vsim.do script
Platform: | Size: 25600 | Author: 许日升 | Hits:

[VHDL-FPGA-Verilog] asyn_fifo

Description: 该源码包是异步fifo的Verilog语言模型，主要包括2个部分：异步fifo控制模块、测试文件。(The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.)
Platform: | Size: 1024 | Author: 叶古 | Hits:

[VHDL-FPGA-Verilog] asyn_fifo

Description: 异步fifo,异步的先进先出，verliog hdl代码，已经经过调试(Asynchronous fifo, asynchronous first out, verliog HDL code, has been debugged)
Platform: | Size: 2048 | Author: 高尔基海燕 | Hits:

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