Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all. Platform: |
Size: 20480 |
Author:daiowen |
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Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived Platform: |
Size: 6144 |
Author:韩冰 |
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Description: This an implementation of an Asynchronous FIFO written in Verilog 2001.-This is an implementation of an Asynchronous FIFO written in Verilog 2001. Platform: |
Size: 2048 |
Author:balloo |
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Description: 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download Platform: |
Size: 25600 |
Author:iechshy1985 |
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Description: 异步FIFO实例，精通verilog hdl中的例子，供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning Platform: |
Size: 2048 |
Author:林 |
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Description: verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time. Platform: |
Size: 1024 |
Author:查乐 |
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Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s
(3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control
Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during
hardware and software flow control. With the FIFO Rdy register, the software gets the
status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide
the user with error indications, operational status, and modem interface control. System
interrupts may be tailored to meet user requirements. An internal loopback capability
allows on-board diagnostics. Platform: |
Size: 160768 |
Author:刘伟 |
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Description: 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out Platform: |
Size: 1024 |
Author:Yongjie |
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Description: 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write an eight-bit data to RAM when the rising edge of read clock pulse, the judge read the signal is valid, from eight bits of data in RAM to a read out. When RAM is full of data to generate a full mark, can not go down RAM write data when the RAM data read empty an empty sign, can not read data from RAM. Platform: |
Size: 333824 |
Author:肖波 |
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Description: 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control Platform: |
Size: 3072 |
Author:zx |
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Description: FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write address lines, very simple to use Platform: |
Size: 14336 |
Author:chenkun |
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Description: 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation Platform: |
Size: 4096 |
Author:T~T |
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Description: Verilog语言写的异步fifo，包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code. I believe you will like it. Platform: |
Size: 27829248 |
Author:allcot |
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Description: 给出一个位宽16比特，深度为10的异步FIFO的设计，并要求给出空或满的指示信号。要求用Verilog HDL语言设计，并编写测试激励，以及用Modelsim进行功能仿真，验证设计正确性。10个16位的数据 (FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它指的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等。FIFO的深度：THE DEEPTH，它指的是FIFO可以存储多少个N位的数据（如果宽度为N）。如一个8位的FIFO，若深度为8，它可以存储8个8位的数据，深度为12，就可以存储12个8位的数据。)-Give a 16 bits wide, depth of 10 asynchronous FIFO design, and requires giving empty or full instructions signal. Request using Verilog HDL language design, and the writing test, and simulation using Modelsim function, validate design is correct. 10 16 bits of data (THE WIDTH of THE FIFO, namely information in English often see THE WIDTH, it refers to a FIFO data read and write operations, as has 8 bit or 16 bit MCU, ARM 32-bit and so on. THE depth of FIFO: THE DEEPTH, it refers to THE FIFO can store many N bits of data (if THE WIDTH is N). If an 8-bit FIFO, if THE depth of 8, it can store 8 8 bits of data, THE depth of 12, 12 8 bits of data to be stored.) Platform: |
Size: 33792 |
Author:江燕子 |
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