Search - atm vhdl

[VHDL-FPGA-Verilog] Cpld

Description: atmel公司arm926 开发办cpld源代码vhdl写的，供大家参考-Atmel CPLD Development Office Company ARM926 VHDL source code written for your information
Platform: | Size: 38912 | Author: 邱劲松 | Hits:

[VHDL-FPGA-Verilog] FT245_R_W

Description: USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.
Platform: | Size: 1644544 | Author: | Hits:

[ELanguage] atm

Description: atm信元检测，CRC循环冗余码编码和校验-atm cell detection, CRC cyclical redundancy check code and
Platform: | Size: 80896 | Author: wh | Hits:

Description: 数据加密算法（Data Encryption Algorithm，DEA）的数据加密标准（Data Encryption Standard，DES）是规范的描述，它出自 IBM 的研究工作，并在 1997 年被美国政府正式采纳。它很可能是使用最广泛的秘钥系统，特别是在保护金融数据的安全中，最初开发的 DES 是嵌入硬件中的。通常，自动取款机（Automated Teller Machine，ATM）都使用 DES。文件是DES代码的VHDL描述 -Data encryption algorithm (Data Encryption Algorithm, DEA) of the Data Encryption Standard (Data Encryption Standard, DES) is a standardized description of it from IBM s research work and, in 1997, formally adopted by the U.S. government. It is probably the most widely used secret key system, especially in protecting the safety of financial data, the initial development of DES is embedded in hardware. Usually, automated teller machines (Automated Teller Machine, ATM) are the use of DES. Document is described in VHDL code DES
Platform: | Size: 676864 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] atm_crc

Description: VHDL function for calculate ATM CRC
Platform: | Size: 1024 | Author: jools | Hits:

[VHDL-FPGA-Verilog] B_PON_OLT_VHDL

Description: ATM-PON(Passive Optical Network) OLT vdhl proj.file
Platform: | Size: 16136192 | Author: mr.jeon | Hits:

[VHDL-FPGA-Verilog] B_PON_ONU_VHDL

Description: ATM-PON ONU vhdl proj. file good luck
Platform: | Size: 6310912 | Author: mr.jeon | Hits:

[Books] Verilogtestbench

Description: 西北工业大学航空微电子中心关于如何写testbench的论文。。论文结合一个ATM测试平台的TESTBENCH设计，讨论了TESTBENCH的结构和总线功能模型（BFM），并对使用 BFM模型进行TESTBENCH设计的策略和方法进行了探讨，希望能对广大设计者有所帮助。-Aviation Microelectronic Center, Northwestern Polytechnical University, testbench on how to write a paper. . Paper combined with a design of ATM test platform TESTBENCH discussed TESTBENCH structure and bus functional model (BFM), and use the BFM model TESTBENCH design strategies and methods Discussed, hoping to help the vast number of designers.
Platform: | Size: 79872 | Author: 高 | Hits:

[LabView] atm-(1)

Description: this simple vhdl code . system of an atm mechine working -this is simple vhdl code . system of an atm mechine working
Platform: | Size: 11264 | Author: Hafeez ur rehman | Hits:

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[VHDL-FPGA-Verilog] Cpld

[VHDL-FPGA-Verilog] FT245_R_W

[ELanguage] atm

[VHDL-FPGA-Verilog] DES101

[VHDL-FPGA-Verilog] atm_crc

[VHDL-FPGA-Verilog] B_PON_OLT_VHDL

[VHDL-FPGA-Verilog] B_PON_ONU_VHDL

[Books] Verilogtestbench

[VHDL-FPGA-Verilog] CaudaldeRedesATM

[VHDL-FPGA-Verilog] atmvhdlcode

[VHDL-FPGA-Verilog] project

[LabView] atm-(1)

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