Search - audio verilog

Search - audio verilog - List

[mpeg mp3] video_compression_systems DL : 0: 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio/video codec
Update : 2025-02-17 Size : 217kb Publisher :
[DSP program] Blackfin_SpeechAudio DL : 0: 在ADI的Blackfin系列DSP上编写的语音＆音频程序-the ADI Blackfin DSP series on the preparation of voice & audio program! !
Update : 2025-02-17 Size : 466kb Publisher : 李里
[VHDL-FPGA-Verilog] I2S DL : 0: 这是一个I2S接口的VHDL实现源代码，I2S是一个通用的音频接口。-This is a I2S interface VHDL source code, I2S is a generic audio interface.
Update : 2025-02-17 Size : 1.51mb Publisher : 孙浩
[ARM-PowerPC-ColdFire-MIPS] AUDIO_DAC DL : 0: 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
Update : 2025-02-17 Size : 2kb Publisher : 赵春生
[Audio program] WM8731 DL : 0: 高品质音频编解码器WM8731的Verilog使用程序。-high-quality audio codec WM8731 Verilog procedures.
Update : 2025-02-17 Size : 7kb Publisher : 李全
[VHDL-FPGA-Verilog] FPGA-based-DAC DL : 1: 用fpga实现的DA转换器，有说明和源码，VDHL文件。 A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The simplest Delta-Sigma DAC consists of a Delta-Sigma modulator and a one bit DAC. Since, both of these components can be realized using digital circuits, it is possible to implement a low precision Delta-Sigma DAC using a PLD.-Using FPGA to achieve the DA converter, has descriptions and source code, VDHL document. A PLD Based Delta-Sigma DACDelta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinaryperformance and low cost of today s audio CDplayers. The simplest Delta-Sigma DAC consists of aDelta-Sigma modulator and a one bit DAC. Since , both of these components can be realized usingdigital circuits, it is possible to implement a lowprecision Delta-Sigma DAC using a PLD.
Update : 2025-02-17 Size : 57kb Publisher : 开心
[VHDL-FPGA-Verilog] DE2_SD_Card_Audio DL : 0: SD卡读取音频数据，由VGA显示。Verilog HDL语言编写，适用DE2实验箱-SD card reader audio data from the VGA display. Verilog HDL language, the application of the experimental box DE2
Update : 2025-02-17 Size : 3kb Publisher : 白雪
[VHDL-FPGA-Verilog] DE2_WEB DL : 1: 用DE2板子实现的音频分析器,需要安装quartus2,硬件需要DE2的板子-DE2 board using the Audio Analyzer realize the need to install quartus2, the hardware needs of the DE2 board
Update : 2025-02-17 Size : 8.23mb Publisher : 任迎
[VHDL-FPGA-Verilog] S12_AudioLoopback_DAV_MIC DL : 0: 从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code
Update : 2025-02-17 Size : 2.3mb Publisher : zl.yin
[VHDL-FPGA-Verilog] DecoderAudio DL : 1: 本程序为SDI的音视频分离Verilog程序，信号通过分离后，可以分离出视频和音频信号。-This procedure for the separation of SDI audio and video Verilog program, the signal after the separation, can be isolated video and audio signals.
Update : 2025-02-17 Size : 2kb Publisher : 邢占鹏
[Audio program] audio_up8sample DL : 0: verilog代码。利用音频信号上采样8倍，然后对audio做pwm调制。-verilog code.upsample audio date 8 times and output pwm of audio.
Update : 2025-02-17 Size : 11kb Publisher : eastwall
[VHDL-FPGA-Verilog] DE2_70_AUDIO DL : 0: 是用VERILOG HDL和NIOS II C/C++ 编的DE2-70板子的音频编解码芯片的使用工程-Is VERILOG HDL and NIOS II C/C++ code of the DE2-70 board in the audio codec chip, the use of project
Update : 2025-02-17 Size : 20.57mb Publisher : 覃建策
[VHDL-FPGA-Verilog] verilog DL : 0: 主要包含了用verilog语言别写的实用于视频例如LCD等显示设备的音频与视频的控制系统，其中包括了延时代码的编写模块，希望对坐显示的有所帮助!-It contains the verilog language with written and practical at the videos of other LCD and other display devices such as audio and video control systems, including the delayed preparation of the code module, want to take display help!
Update : 2025-02-17 Size : 9kb Publisher : 熊文
[VHDL-FPGA-Verilog] ADC DL : 0: a verilog code about dac of audio codec on fpga board.
Update : 2025-02-17 Size : 1kb Publisher : DCLAB
[VHDL-FPGA-Verilog] DAC DL : 0: a verilog code about dac of audio codec on fpga board.
Update : 2025-02-17 Size : 1kb Publisher : DCLAB
[VHDL-FPGA-Verilog] Wolfson-WM8731-audio-CODEC DL : 0: audio codec data sheet
Update : 2025-02-17 Size : 664kb Publisher : Venky
[VHDL-FPGA-Verilog] xapp514_aes3-audio DL : 0: DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
Update : 2025-02-17 Size : 4.28mb Publisher : dcshl
[VHDL-FPGA-Verilog] LIP1759CORE_audio_dsp32_decoder DL : 0: Audio DSP32 Decoder Verilog Module
Update : 2025-02-17 Size : 47kb Publisher : jc
[VHDL-FPGA-Verilog] i2s DL : 1: 用Verilog实现的i2s功能，支持24bit的左右声道接收和发送。左对齐，延迟1拍。(I2S module, Verilog I2S, up to 24-Bit Data Data Valid on Rising Edge of SCLK)
Update : 2025-02-17 Size : 8kb Publisher : zlh840
[VHDL-FPGA-Verilog] Verilog DL : 0: aes digital audio interface from xilinx
Update : 2025-02-17 Size : 48kb Publisher : SiamackBM

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