Search - avalon bus

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[VHDL-FPGA-Verilog] Avalon_VGA DL : 0: Avalon_VGA，-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.-Avalon_VGA.-- This design provides an interface to the Alca hest VGA daughter card.-- The design comprises of an 8-bit VGA driver with Avalon bus interface s. There are a total of-- three Avalon interface s.
Update : 2025-03-14 Size : 16kb Publisher : 陈朋
[VHDL-FPGA-Verilog] altera_lcd_controller DL : 0: quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
Update : 2025-03-14 Size : 26kb Publisher : 张建
[Embeded-SCM Develop] Avalon_Bus_Specification DL : 0: Avalon Bus的参考手册.对做nios的sopc的人很有参考价值.-Avalon Bus reference manual. To do the Nios SOPC people could very well refer.
Update : 2025-03-14 Size : 1.34mb Publisher : 张大海
[VHDL-FPGA-Verilog] generic_avalon_sram DL : 0: 一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.
Update : 2025-03-14 Size : 5kb Publisher : 林盈
[VHDL-FPGA-Verilog] altera_avalon_checksum DL : 0: altera的avalon总线校验代码,是进行sopc开发的参考-altera the avalon bus check code, is to develop a reference SOPC
Update : 2025-03-14 Size : 12kb Publisher : 钟兵
[VHDL-FPGA-Verilog] Avalon DL : 0: Avalon总线规范的简单介绍-Avalon Bus Specification, a simple introduction
Update : 2025-03-14 Size : 4.43mb Publisher : 付茗
[VHDL-FPGA-Verilog] xd_lcd_comp DL : 0: 一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
Update : 2025-03-14 Size : 13kb Publisher : 张敏
[ARM-PowerPC-ColdFire-MIPS] Avalon DL : 0: Avalon 总线规范中文，详细描述，入门好材料-Avalon Bus Specification, Chinese, detailed description, entry-good material
Update : 2025-03-14 Size : 410kb Publisher : 王之希
[VHDL-FPGA-Verilog] Avalon_PWM_IP_pwm DL : 0: Avalon总线下的PWM的IP模块。基于VHDL语言。-Avalon Bus IP of the PWM module. Based on the VHDL language.
Update : 2025-03-14 Size : 20kb Publisher : 李超
[VHDL-FPGA-Verilog] DE2_pio DL : 0: altera University Program 的 Avalon总线的IP核，GPIO，可以直接解压以后挂载在Avalon总线上-altera University Program of the Avalon bus IP core, GPIO, after decompression can be directly mounted in the Avalon bus
Update : 2025-03-14 Size : 265kb Publisher : vicky
[Program doc] AVALON-BUS-Specification DL : 0: AVALON BUS Specification,AVALON总线英文完整规范-AVALON BUS Specification, AVALON bus full specification in English
Update : 2025-03-14 Size : 1.34mb Publisher : 行路人
[Embeded-SCM Develop] 1 DL : 0: Avalon总线的pwm定制，在niosII下定制了PWM通过avalon总线链接到niosII上，绝非一般的实验，应用在实际的工控项目中。-Avalon bus pwm custom, under the custom of the PWM in the niosII by avalon bus link to niosII on the experiment in general not applied in real industrial control projects.
Update : 2025-03-14 Size : 571kb Publisher : 陈泸华
[Other] Avalon_uSequencer DL : 0: 用于控制Altera Avalon总线设备的一个微型的状态机，可以运行类似汇编语言的Script，比Nios II CPU占用的资源少许多，可以生成明文的源代码-A tiny state machine used to control Altera Avalon bus devices. It can run script language similar to the assembly , occupied much less cells than the Nios II CPU resources. It can generate un-encrypted source code
Update : 2025-03-14 Size : 34.2mb Publisher : Joe
[SCM] LED DL : 0: 本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA 公司的 Cyclone II 系列 FPGA 为数字平台，将微处理器、Avalon 总线、LED 点阵扫描控制器、存储器和人机接口控制器等硬件设备集中在一片 FPGA 上，利用片内硬件来实现 LED 点阵的带地址扫描，降低系统总功耗和简化 CPU 编程的同时，提高了系统的精确度、稳定性和抗干扰性能。-This design used the Nios II embedded processor based on SOPC technology. System to ALTERA' s Cyclone II series FPGA for digital platforms, microprocessors, Avalon bus, LED dot matrix scan controller, memory and man-machine interface controller and other hardware devices focused on an FPGA, using on-chip hardware to achieve the LED dot-matrix band address scan, reducing the total system CPU power consumption and simplify programming while increasing the system' s accuracy, stability and anti-jamming performance.
Update : 2025-03-14 Size : 946kb Publisher : 叶子
[Windows Develop] Avalon DL : 0: Avalon 总线规范中文，详细描述，入门好材料-Avalon Bus Specification Chinese, detailed description of the good stuff started
Update : 2025-03-14 Size : 410kb Publisher : 張三
[VHDL-FPGA-Verilog] Template_Slave DL : 0: avalon总线的从端口实例代码，简单，易懂，方便初学者学习。-avalon bus example code from the port, simple, easy to understand, easy for beginners to learn.
Update : 2025-03-14 Size : 9kb Publisher : 穆屹峰
[VHDL-FPGA-Verilog] Nios-textbook DL : 0: 针对nios环境开发进行了详细地讲解，包括sopc，外设，avalon总线等。-Nios environment for the development were explained in detail, including sopc, peripherals, avalon bus and so on.
Update : 2025-03-14 Size : 3.45mb Publisher : 魏丽娟
[Software Engineering] Avalon-bus DL : 0: Avalon总线综述，介绍Avalon总线规范及协议-Avalon BUS
Update : 2025-03-14 Size : 452kb Publisher : qulong
[VHDL-FPGA-Verilog] Avalon---TFT-LCD- DL : 0: 基于Avalon总线的TFT LCD 控制器的设计-Avalon bus-based controller design of TFT LCD
Update : 2025-03-14 Size : 140kb Publisher : 刘小瑜
[Software Engineering] wishbone-slave-and-master-to-avalon-bus DL : 0: wishbone slave and master to avalon bus verilog
Update : 2025-03-14 Size : 1kb Publisher : lamqsb

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