Search - avalon bus

[VHDL-FPGA-Verilog] Avalon_VGA

Description: Avalon_VGA，-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.-Avalon_VGA.-- This design provides an interface to the Alca hest VGA daughter card.-- The design comprises of an 8-bit VGA driver with Avalon bus interface s. There are a total of-- three Avalon interface s.
Platform: | Size: 16384 | Author: 陈朋 | Hits:

[VHDL-FPGA-Verilog] altera_lcd_controller

Description: quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
Platform: | Size: 26624 | Author: 张建 | Hits:

[Embeded-SCM Develop] Avalon_Bus_Specification

Description: Avalon Bus的参考手册.对做nios的sopc的人很有参考价值.-Avalon Bus reference manual. To do the Nios SOPC people could very well refer.
Platform: | Size: 1409024 | Author: 张大海 | Hits:

[VHDL-FPGA-Verilog] generic_avalon_sram

Description: 一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.
Platform: | Size: 5120 | Author: 林盈 | Hits:

[VHDL-FPGA-Verilog] altera_avalon_checksum

Description: altera的avalon总线校验代码,是进行sopc开发的参考-altera the avalon bus check code, is to develop a reference SOPC
Platform: | Size: 12288 | Author: 钟兵 | Hits:

[VHDL-FPGA-Verilog] Avalon

Description: Avalon总线规范的简单介绍-Avalon Bus Specification, a simple introduction
Platform: | Size: 4641792 | Author: 付茗 | Hits:

[VHDL-FPGA-Verilog] xd_lcd_comp

Description: 一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
Platform: | Size: 13312 | Author: 张敏 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Avalon

Description: Avalon 总线规范中文，详细描述，入门好材料-Avalon Bus Specification, Chinese, detailed description, entry-good material
Platform: | Size: 419840 | Author: 王之希 | Hits:

[VHDL-FPGA-Verilog] Avalon_PWM_IP_pwm

Description: Avalon总线下的PWM的IP模块。基于VHDL语言。-Avalon Bus IP of the PWM module. Based on the VHDL language.
Platform: | Size: 20480 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] DE2_pio

Description: altera University Program 的 Avalon总线的IP核，GPIO，可以直接解压以后挂载在Avalon总线上-altera University Program of the Avalon bus IP core, GPIO, after decompression can be directly mounted in the Avalon bus
Platform: | Size: 271360 | Author: vicky | Hits:

[Program doc] AVALON-BUS-Specification

Description: AVALON BUS Specification,AVALON总线英文完整规范-AVALON BUS Specification, AVALON bus full specification in English
Platform: | Size: 1406976 | Author: 行路人 | Hits:

[Embeded-SCM Develop] 1

Description: Avalon总线的pwm定制，在niosII下定制了PWM通过avalon总线链接到niosII上，绝非一般的实验，应用在实际的工控项目中。-Avalon bus pwm custom, under the custom of the PWM in the niosII by avalon bus link to niosII on the experiment in general not applied in real industrial control projects.
Platform: | Size: 584704 | Author: 陈泸华 | Hits:

[Other] Avalon_uSequencer

Description: 用于控制Altera Avalon总线设备的一个微型的状态机，可以运行类似汇编语言的Script，比Nios II CPU占用的资源少许多，可以生成明文的源代码-A tiny state machine used to control Altera Avalon bus devices. It can run script language similar to the assembly , occupied much less cells than the Nios II CPU resources. It can generate un-encrypted source code
Platform: | Size: 35857408 | Author: Joe | Hits:

[SCM] LED

Description: 本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA 公司的 Cyclone II 系列 FPGA 为数字平台，将微处理器、Avalon 总线、LED 点阵扫描控制器、存储器和人机接口控制器等硬件设备集中在一片 FPGA 上，利用片内硬件来实现 LED 点阵的带地址扫描，降低系统总功耗和简化 CPU 编程的同时，提高了系统的精确度、稳定性和抗干扰性能。-This design used the Nios II embedded processor based on SOPC technology. System to ALTERA' s Cyclone II series FPGA for digital platforms, microprocessors, Avalon bus, LED dot matrix scan controller, memory and man-machine interface controller and other hardware devices focused on an FPGA, using on-chip hardware to achieve the LED dot-matrix band address scan, reducing the total system CPU power consumption and simplify programming while increasing the system' s accuracy, stability and anti-jamming performance.
Platform: | Size: 968704 | Author: 叶子 | Hits:

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[VHDL-FPGA-Verilog] Avalon_VGA

[VHDL-FPGA-Verilog] altera_lcd_controller

[Embeded-SCM Develop] Avalon_Bus_Specification

[VHDL-FPGA-Verilog] generic_avalon_sram

[VHDL-FPGA-Verilog] altera_avalon_checksum

[VHDL-FPGA-Verilog] Avalon

[VHDL-FPGA-Verilog] xd_lcd_comp

[ARM-PowerPC-ColdFire-MIPS] Avalon

[VHDL-FPGA-Verilog] Avalon_PWM_IP_pwm

[VHDL-FPGA-Verilog] DE2_pio

[Program doc] AVALON-BUS-Specification

[Embeded-SCM Develop] 1

[Other] Avalon_uSequencer

[SCM] LED

[Windows Develop] Avalon

[VHDL-FPGA-Verilog] Template_Slave

[VHDL-FPGA-Verilog] Nios-textbook

[Software Engineering] Avalon-bus

[VHDL-FPGA-Verilog] Avalon---TFT-LCD-

[Software Engineering] wishbone-slave-and-master-to-avalon-bus

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