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[VHDL-FPGA-Verilog] CODE

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram verilog
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[VHDL-FPGA-Verilog] BP062-BU-01000-r0p0-00rel0[1][1].tar

Description: AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
Platform: | Size: 313344 | Author: 李忠孝 | Hits:

[VHDL-FPGA-Verilog] handshake

Description: AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
Platform: | Size: 196608 | Author: nodeity | Hits:

[VHDL-FPGA-Verilog] ppt

Description: 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
Platform: | Size: 637952 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] eetop[1].cn_axibusregslice

Description: axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
Platform: | Size: 2048 | Author: 林启明 | Hits:

[VHDL-FPGA-Verilog] src

Description: AXI Slave codes in verilog. Downloded from www.opencores.org free download
Platform: | Size: 17408 | Author: Shibin Bose K | Hits:

[Driver Develop] AXI_slave

Description: 自己写的 AXI slave 代码，是ARM 内嵌的 总线通信-AXI slave code
Platform: | Size: 922624 | Author: redleaf | Hits:

[Other] AXI-HP-PDMAPGIC

Description: 本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。 本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目 的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。-This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.
Platform: | Size: 801792 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] AXI slave

Description: 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
Platform: | Size: 1024 | Author: 天地孤影i | Hits:

[VHDL-FPGA-Verilog] slave

Description: xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
Platform: | Size: 1024 | Author: wd小强 | Hits:

[VHDL-FPGA-Verilog] axi_slave

Description: amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
Platform: | Size: 1024 | Author: 过客3944 | Hits:

[Other] new.v

Description: 状态机写的axi slave，模式较少，基本功能齐全，轻便,仿真综合通过(AXI4 slave programmed by state machine approach)
Platform: | Size: 1024 | Author: 风城复辟 | Hits:

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