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[ARM-PowerPC-ColdFire-MIPS] 081002026_Vishnuvardhan

Description: AMBA AXI4-Lite is an fourth generation interface released by ARM on 03rd march 2010
Platform: | Size: 326656 | Author: vishnu | Hits:

[VHDL-FPGA-Verilog] Axi4

Description: Dynamic routing is desirable because of its substantial improvement in communication bandwidth and intelligent adaptation to faulty links and congested traffic. However, implementation of adaptive routing in a network-on-chip system is not trivial and is further complicated by the requirements of deadlock-free and real-time optimal decision making.
Platform: | Size: 3072 | Author: Paul Stephen | Hits:

[VHDL-FPGA-Verilog] ppt4aix4sopc

Description: 基于AXI4的sopc开发讲义,2011年电子大赛的辅导材料-powerpoint for aix4 sopc development
Platform: | Size: 1261568 | Author: sunking | Hits:

[VHDL-FPGA-Verilog] AxiPC

Description: fpga axi测试程序,可测试符合axi协议的ip核-fpga AXI4 TEST routine，can be used to test ip which is in amba.
Platform: | Size: 24576 | Author: zyy | Hits:

[VHDL-FPGA-Verilog] ppt

Description: 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
Platform: | Size: 637952 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] axi4-checker

Description: ARM公司官方的AXI4总线的SVA检测。带完整说明文档，AXI4，AXI4-Lite，AXI4-Stream协议均已经包含-ARM s official AXI4 bus SVA testing. With complete documentation, AXI4, AXI4-Lite, AXI4-Stream protocol are already included
Platform: | Size: 454656 | Author: Linear | Hits:

[Program doc] amba

Description: Amba AXI4 Standards, Amba AXI4-Lite, Amba AXI4-Stream
Platform: | Size: 2772992 | Author: nohous | Hits:

[Special Effects] LogiCORE-IP-Video-Scaler-v4.0

Description: The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. System design is made easier through support of both streaming-video and frame buffer-based interfaces. This core is designed to connect via an AXI4-Lite interface.-The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. System design is made easier through support of both streaming-video and frame buffer-based interfaces. This core is designed to connect via an AXI4-Lite interface.
Platform: | Size: 1171456 | Author: JackTong | Hits:

[VHDL-FPGA-Verilog] ds769_axi_slave_burst

Description: xilinx AXI4 slave burst 接口的介绍文档，有助于理解IP核-The introduction of xilinx AXI4 slave into the interface documentation
Platform: | Size: 1714176 | Author: 李疯子 | Hits:

[VHDL-FPGA-Verilog] demo4

Description: AXI4-stream协议，用于调试，测试代码，IPcore-The AXI4-stream protocol, used to debug, test code, IPcore
Platform: | Size: 24576 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] tb_axi4

Description: 介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。-It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.
Platform: | Size: 142336 | Author: 岑家俊 | Hits:

[Software Engineering] axi_ipif_v2.3

Description: LogiCORE IP AXI4-Lite IPIF
Platform: | Size: 404480 | Author: pong hk | Hits:

[Software Engineering] axi-timer

Description: 这是Xilinx AXI定时器的说明手册，对于进行FPGA开发的工程师有参考价值 -The LogiCORE IP AXI Timer/Counter is a 32/ 64-bit timer module that interfaces to the AXI4-Lite interface.
Platform: | Size: 434176 | Author: bill zhao | Hits:

[VHDL-FPGA-Verilog] axi3_axi4_perfect

Description: 介绍AMBA，axi3 与 axi4的一些基本知识，并详细介绍了传输特性(Introduction to AMBA. Some features between axi3 and axi4 and transfer features)
Platform: | Size: 953344 | Author: 疯释怀 | Hits:

[MPI] gate_test

Description: 使用vivado hls 对GATE代码进行封装，主要调试stream接口(using vivado hls to archieve GATE syn, to debug the AXI4-stream interface)
Platform: | Size: 2184192 | Author: beny270 | Hits:

[Other] AXI4与AXI3的区别

Description: AXI4与AXI3的区别,l例如：AXI4对burst length进行了扩展：AXI3最大burst length是16 beats,而AXI4支持最大到256 beats，但是仅支持INCR burst type超过16 beats，exclusive access也不能超过16beats;。(the different of AXI4 and AXI3)
Platform: | Size: 22528 | Author: 拓天疆 | Hits:

[VHDL-FPGA-Verilog] master_slave

Description: AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
Platform: | Size: 12478464 | Author: Zhongzi123 | Hits:

[VHDL-FPGA-Verilog] package_control-master

Description: 从github下载的，能够参考设计AXI4的协议接口(AXI4 Verilog template)
Platform: | Size: 461824 | Author: danieltang | Hits:

[Other] AMBA-AXI3-master (1)

Description: AXI4 verification and design using verilog.
Platform: | Size: 4137984 | Author: workaholic | Hits:

[Other] AXI4学习

Description: 关于XILLINX的AXI4总线协议的学习(Learning about XILLINX AXI4 Bus Protocol)
Platform: | Size: 1969152 | Author: gp2067 | Hits:
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