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[Other resource] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2015 | Author: wyl | Hits:

[Other resource] BFM_design_material

Description: bfm（总线功能模型）设计的基础教材，值得一看，需要lotus打开文档-BFM (bus functional model) designed on the basis materials, an eye-catcher, Lotus needs to open files
Platform: | Size: 52279 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[Other] BFM_design_material

Description: bfm（总线功能模型）设计的基础教材，值得一看，需要lotus打开文档-BFM (bus functional model) designed on the basis materials, an eye-catcher, Lotus needs to open files
Platform: | Size: 52224 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] ata.tar

Description: 硬盘接口的硬件实现，VHDL和Verilog是吸纳的，带有文档！-Hard disk interface hardware implementation, VHDL and Verilog is absorbed with documentation!
Platform: | Size: 832512 | Author: 刘志刚 | Hits:

[Program doc] TheResearchAndIPDesignOfSMBusBasedSmartBattery

Description: 本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台 完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有 良好的性能。-This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.
Platform: | Size: 256000 | Author: caorui | Hits:

[Database system] datalist

Description: 利用datalist控件绑定数据库里的数据-bfm
Platform: | Size: 1024 | Author: 刘强 | Hits:

[Books] Verilogtestbench

Description: 西北工业大学航空微电子中心关于如何写testbench的论文。。论文结合一个ATM测试平台的TESTBENCH设计， 讨论了TESTBENCH的结构和总线功能模型（BFM） ， 并对使用 BFM模型进行TESTBENCH设计的策略和方法 进行了探讨， 希望能对广大设计者有所帮助。-Aviation Microelectronic Center, Northwestern Polytechnical University, testbench on how to write a paper. . Paper combined with a design of ATM test platform TESTBENCH discussed TESTBENCH structure and bus functional model (BFM), and use the BFM model TESTBENCH design strategies and methods Discussed, hoping to help the vast number of designers.
Platform: | Size: 79872 | Author: 高 | Hits:

[matlab] BFM

Description: 两个16个阵元的平面阵波束形成。很好用的-16 element array of two plane array beamforming. Very good use
Platform: | Size: 1024 | Author: hanchao | Hits:

[VHDL-FPGA-Verilog] bfm

Description: Bus Functional Model Design
Platform: | Size: 2048 | Author: Yak | Hits:

[Other] Datcom99_input_BFM

Description: A input file for Datcom99.It's a model of BFM.BFM is usually used to verify the numerical method of N-S Equation.Also ,I put my result in the zip.(A input file for Datcom99.It's a model of BFM.BFM is usually used to verify the numerical method of N-S Equation.)
Platform: | Size: 9216 | Author: Icaros | Hits:

[Other] CoreAMBA_BFM_UG

Description: 用AMBA主从功能仿真的指令详细描述，非常简单。(CORETEX-M3 AMBA BFM simulation)
Platform: | Size: 827392 | Author: hongbachelor | Hits:

[Program doc] pfsoc_mss_sim_ug

Description: The PolarFire SoC FPGA's Microcontroller Subsystem (MSS) is modeled with Microsemi's AMBA Bus Functional Model (BFM) and it is limited at FIC itself. For information about the supported instructions and syntax of the BFM commands, refer to the Microsemi DirectCore AMBA BFM User's Guide.
Platform: | Size: 398639 | Author: jiangtq | Hits:

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