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[VHDL-FPGA-Verilog] resolutionquartusII

Description: 用verilog编写的分辨率提高的源代码 采用双线性插值-Written resolution with the verilog source code to improve the use of bilinear interpolation
Platform: | Size: 6241280 | Author: 权晶 | Hits:

[Special Effects] video_stream_scaler

Description: Verilog HDL实现双线性插值视频实时缩放，源码及说明文档-Verilog HDL bilinear interpolation real-time zoom, video source and documentation
Platform: | Size: 5643264 | Author: | Hits:

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