Description: EDA实验：掌握使用VHDL 描述组合电路的基本方法，学会使用QuatusII 对VHDL 代码进行综合和仿真，能够使用时序仿真功能对所设计模块进行仿真测试。（四位二进制数比较器 序列信号发生器 十字路口交通灯的设计）-EDA experiment: to master the combination of the circuit VHDL description of the basic methods, learn to use QuatusII of the VHDL code synthesis and simulation, timing simulation function can be used by the design module of the simulation test. (4 binary sequence generator comparator design of intersection traffic lights) Platform: |
Size: 906240 |
Author:马琳 |
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Description: 设计模式比较器电路：电路的输入为两个8位无符号二进制数a、b和一个模式控制信号m；电路的输出为8位无符号二进制数y。当m=0时，y=MAX(a,b) 而当m=1时，则y=MIN(a,b)。要求用多层次结构设计电路，即调用数据选择器和比较器等基本模块来设计电路。-Design pattern comparator circuit: circuit input as two 8-bit unsigned binary numbers a, b and a mode control signal m circuit output is 8-bit unsigned binary number y. When when m = 0, y = MAX (a, b) and when m = 1, then y = MIN (a, b). Requires a multi-level structure design circuits that call data selector and comparators basic modules to design circuits. Platform: |
Size: 1024 |
Author:Peter |
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Description: 设计一个一位二进制数大小比较器。比较两个一位二进制数A和B的大小，电路有三个输出端Y1，Y2和Y3，分别对应A大于B，A等于B，A小于B。当条件满足时，相应输出端为1，否则为0。（A，B用两个脉冲源代替），建立仿真模型并保存。-Design a one binary magnitude comparator. A size comparison of two binary numbers A and B, the circuit has three outputs Y1, Y2 and Y3, respectively, corresponding to the A greater than B, A is equal to B, A less than B. When the conditions are met, the corresponding output is 1, and 0 otherwise. (A, B instead of the source with two pulses), and save the simulation model. Platform: |
Size: 7168 |
Author:tx |
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Description: 设计一个两位二进制数大小比较器。要求当二进制数A=A1A0大于二进制数B=B1B0时，电路输出为1，否则为0（A1，A0，B1，B0用四个脉冲源代替），建立仿真模型并保存。-Design a two binary magnitude comparator. Required when the binary number is greater than the binary number A = A1A0 B = B1B0, the circuit output is 1, otherwise 0 (A1, A0, B1, B0 in place with four pulse sources), and save the simulation model. Platform: |
Size: 5120 |
Author:tx |
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Description: Logisim四位排序器
先使用1位的swap搭建4位的swap，再使用4位的swap模块和Logisim内置的comparator元件搭建排序电路(请不要使用Plexers类元件)
功能描述:该电路具有4个4位的二进制数字作为输入和4个4位的二进制数字作为输出。它的功能是，将4个输入的二进制数字进行排序，从上往下数第一个输出端口输出的是4个数字中最小的，第二个输出端口输出的是第二小的，以此类推。
输入： A,B,C,D(4bit)
输出： #1,#2,#3,#4(4bit)(#1对应第一个输出端口，以此类推)
文件内 1 位swap模块名: 1bit_swap
文件内 4 位swap模块名: 4bit_swap
文件内 排序电路模块名: 4bit_sort(Logisim four bit sorter
Build a 4-bit swap using a 1-bit swap, and a sort circuit using a 4-bit swap module and a built-in comparator component in Logisim (do not use Plexers class components)
Function Description: The circuit has four 4-bit binary digits as input and four 4-bit binary digits as output. Its function is to sort the four input binary digits. The output from the first output port is the smallest of the four digits, the output from the second output port is the second smallest, and so on.
Input: A, B, C, D (4bit)
Output: #1, #2, #3, #4 (4bit) (#1 corresponds to the first output port, and so on).
The 1 bit swap module name in the file is 1bit_swap
The 4 bit swap module name in the file is 4bit_swap
File sorting circuit module name: 4bit_sort) Platform: |
Size: 2048 |
Author:deathpool |
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Search - binary comparator circuit