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[Other] Some_VHDL_Examples

Description: 几个VHDL的例子，供大家参考，包括寄存器的设计，同步二进制计数器的设计，时钟计数器的设计等，个人觉得很有用处-Several examples of VHDL for reference, including the register of designs, synchronous binary counter design, the design of the clock counter, personal feel that is very useful
Platform: | Size: 168960 | Author: 钱 | Hits:

[VHDL-FPGA-Verilog] binarycount

Description: 异步复位、同步置数的四位二进制计数器的VHDL源文件-Asynchronous reset, synchronous purchase the number of binary counter 4 of the VHDL source files
Platform: | Size: 1024 | Author: chenwen | Hits:

[Windows Develop] 11

Description: cnt6.bdf 六进制约翰逊计数器 counters.vhd 不同功能的简单计数器 count60.vhd 60进制计数器 count60.bdf 60进制计数器 counter_1024.vhd 8位二进制计数器 counter_1m.vhd 16位二进制计数器 counter.vhd N进制计数器-M Johnson cnt6.bdf six different functions counters.vhd counter simple counter count60.vhd 60 hexadecimal counter count60.bdf 60 hexadecimal counter counter_1024.vhd 8 bit binary counter counter_1m.vhd 16 bit binary counter counter.vhd N M-ary Counter
Platform: | Size: 7168 | Author: libing | Hits:

[VHDL-FPGA-Verilog] count_binary_0

Description: 二进制计数器的硬件代码，可在ISE或quartus下完成调试-Binary counter hardware code, available at ISE or Quartus to complete debugging
Platform: | Size: 9216 | Author: | Hits:

[Windows Develop] counter

Description: 详细描述n比特计数器及RTL验证，计数器的位宽用generic语句设置为参数。MY_CNTR是一个n比特二进制的计数器，可以向上向下计数，并可设置计数值，计数器用异步的方式进行低电平复-A detailed description of n-bit counter and RTL verification, the bit counter is set to use generic parameters statement. MY_CNTR is an n-bit binary counter, counting down to up, and set of values, counters with asynchronous low-level approach to rehabilitation
Platform: | Size: 10240 | Author: chixiaobin | Hits:

[VHDL-FPGA-Verilog] counter

Description: It s a binary counter
Platform: | Size: 1024 | Author: gegry | Hits:

[Software Engineering] Counter

Description: 所谓24进制计数器,要在数码管上直观的显示0,1…..22,23等数,再归零-The so-called binary counter 24 to the digital control on the visual display 0,1 ... .. 22,23 and a few, then zero
Platform: | Size: 121856 | Author: xiejun | Hits:

[SCM] counter

Description: 任意多进制计数器，可以进行计数，制定进制数然后计数。也可以进行移位显示。-Any number of binary counter can count, then count the number of developing band. Shift can also be displayed
Platform: | Size: 1024 | Author: lixun2006217 | Hits:

[VHDL-FPGA-Verilog] counter

Description: 这是带清零端的8位二进制计数器，是用verilog hdl语言编写的-This is the side with a clear 8-bit binary counter, is written with the verilog hdl
Platform: | Size: 19456 | Author: 郭小 | Hits:

[VHDL-FPGA-Verilog] counter

Description: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
Platform: | Size: 1024 | Author: jgc | Hits:

[VHDL-FPGA-Verilog] counter

Description: N-bit binary counter using behavioral model
Platform: | Size: 1024 | Author: xaminx | Hits:

[VHDL-FPGA-Verilog] 10-binary-counter

Description: 使用verilog实现10进制计数器功能,可以实现Quartus仿真，含任意进制计数器程序-10 binary counter using verilog implementation function, can realize Quartus simulation program with an arbitrary binary counter
Platform: | Size: 13312 | Author: lizhengye | Hits:

[Software Engineering] 8-jinzhi-counter

Description: 8进制计数器 每计数八次进一次位，vhdl语言的基础程序，对初学者很有帮助-8 binary counter into a bit of each of eight counts, vhdl language based program, very helpful for beginners
Platform: | Size: 1024 | Author: zhaohong | Hits:

[Software Engineering] 10-jinzhi-counter

Description: 10进制计数器 每计数十次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Total scores of 10 binary counter has a per carry, is the basis for vhdl programming procedures used in programmable logic devices fpga cpld
Platform: | Size: 1024 | Author: zhaohong | Hits:

[assembly language] design-a-decade-counter

Description: 设计一个四位二进制计数器，将计数结果由数码管显示，显示结果为十进制数。数码管选通为低电平有效，段码为高电平有效。-The design of a four-bit binary counter will count digital display, and displays the results as a decimal number. Digital tube strobe active-low segment code for active high.
Platform: | Size: 15360 | Author: jingzai | Hits:

[VHDL-FPGA-Verilog] VHDL-Binary-counter

Description: Binary counter, its used to count the numbers in binary format
Platform: | Size: 14336 | Author: Charles | Hits:

[Other] binary-counter

Description: 此文件为Altium Designer Summer 09中二进制计数器的源程序，欢迎大家参阅。-This file Altium Designer Summer 09 binary counter source, welcomed everyone to see.
Platform: | Size: 75776 | Author: 王黎明 | Hits:

[LabView] Binary-counter-experiment

Description: 利用NI ELVIS平台搭建电路，运用Labview编程，设计一个二进制计数器。-Use NI ELVIS platform to build circuits using Labview programming, design a binary counter.
Platform: | Size: 122880 | Author: 梁月仙 | Hits:

[VHDL-FPGA-Verilog] Johnaon_counter

Description: 本设计为六位约翰逊(Johnson)计数器，首先给大家介绍一下什么是约翰逊计数器，它又称扭环计数器,是一种用n位触发器来表示2n个状态的计数器。它与环形计数器不同,后者用n位触发器仅可表示n个状态。2~n进制计数器(n为触发器的个数)有2~n个状态。若以6位二进制计数器为例,它可表示64个状态。但由于8421码每组代码之间可能有二位或二位以上的二进制代码发生改变,这在计数器中特别是异步计数器中就有可能产生错误的译码信号,从而造成永久性的错误。而约翰逊计数器的状态表中,相邻两组代码只可能有一位二进制代码不同,故在计数过程中不会产生错误的译码信号。鉴于上述优点,约翰逊计数器在同步计数器中应用比较广泛。(This design is a six-bit Johnson counter, first of all to introduce what is the Johnson counter, it also called the torsion ring counter, is a kind of n-bit trigger to represent the 2n state of the counter. It differs from a ring counter, which uses n-bit triggers only to represent N states. The 2~n feed counter (n is the number of triggers) has a 2~n state. For example, a 6-bit binary counter can represent 64 states. However, because there may be two-bit or more than two bits of binary code between each set of code in 8421 yards, it is possible to produce the wrong decoding signal in the counter, especially in the asynchronous counter, resulting in a permanent error. In the state table of the Johnson counter, the adjacent two groups of code may only have one binary code, so there will be no wrong decoding signal in the counting process. In view of the above advantages, Johnson counter is widely used in synchronization counter.)
Platform: | Size: 6144 | Author: Leegege | Hits:

[VHDL-FPGA-Verilog] bcd counter

Description: Binary counter design in verilog
Platform: | Size: 176128 | Author: Armaghan | Hits:
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