Description: 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock Platform: |
Size: 3152400 |
Author:Jawen |
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Description: convert.asm:
1.From ASCII resp. BCD to binary
2.From binary to ASCII resp. BCD
3.From binary to Hex-ASCII
Bin_Bcd.c:
uchar BcdToBin(uchar val)
uchar BinToBcd(uchar val) -convert.asm : 1.From ASCII resp. BCD 2.From binary to binary t o ASCII resp. BCD 3.From binary to Hex-ASCII Bin _Bcd.c : uchar BcdToBin (uchar val) uchar BinToBcd (uch ar val) Platform: |
Size: 5120 |
Author:jack |
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Description: 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock Platform: |
Size: 3151872 |
Author:Jawen |
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Description: General Binary-to-BCD Converter
The linked code is a general binary-to-BCD Verilog module, and I have personally tested the code. Platform: |
Size: 25600 |
Author:volkan |
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Description: 一个用Verilog语言实现的二进制码到BCD码的一种转换方法的实现。包含工程文件和实现文档。-Verilog language implementation with a binary code to BCD code conversion method as a realization. And the achievement of the document contains the project file. Platform: |
Size: 82944 |
Author:文闯 |
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Description: this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder-this is a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder Platform: |
Size: 1024 |
Author:hassan |
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Description: This is a binary to BCD convert designed by using the “shift and add-3 algorithm”. The verilog code of basic cell add-3 is also included in this file. Platform: |
Size: 9216 |
Author:WPI |
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Description: 二进制转BCD的verilog程序,实现二进制数到BCD的转换,该程序具有节约FPGA的内部逻辑资源等特点-
Binary to BCD s verilog procedures to achieve binary number to BCD conversion, the program has an internal FPGA logic resources saving features Platform: |
Size: 458752 |
Author:宋国志 |
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Description: 多种基本功能的Verilog代码实现,包括多路选择器,二进制到BCD码转换,二进制到格雷码转换,7段译码器,8位数据锁存器,移位寄存器等等多种功能。(Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit data latch, shift register and many other functions.) Platform: |
Size: 18432 |
Author:MMK1 |
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