Description: 用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources. Platform: |
Size: 1024 |
Author:yato_logo |
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Description: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as Platform: |
Size: 82944 |
Author:lkiwood |
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Description: 系统设置一个两位BCD码倒计时计数器（计数脉冲1HZ），用于记录各状态持续时间；
因为各状态持续时间不一致，所以上述计数器应置入不同的预置数；
倒计时计数值输出至二个数码管显示；
程序共设置4个进程：
① 进程P1、P2和P3构成两个带有预置数功能的十进制计数器，其中P1和P3分别为个位和十位计数器，P2产生个位向十位的进位信号；
② P4是状态寄存器，控制状态的转换，并输出6盏交通灯的控制信号。-System to set up a two BCD code countdown counter (count pulse 1HZ), used to record the duration of each state because the duration of each state are inconsistent, so these counters should be placed in several different presets countdown of numerical output to two digital display procedures were set up four processes: ① process P1, P2 and P3 form two functions with a preset number of decimal counters, of which P1 and P3, respectively, for months, and 10-bit counters, P2 to generate a 10-bit The binary signal ② P4 is the status register, control the state of the conversion, and six output control signals of traffic lights. Platform: |
Size: 1024 |
Author:kid |
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Description: 一个用VHDL语言编写的十进制计数器，后续还有分频器、数据选择器、七段数码显示程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -VHDL language using a decimal counter, follow-up there is divider, data selector, seven-segment digital display procedures, the software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and interest in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157 Platform: |
Size: 242688 |
Author:QQ |
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Description: 数据存储和读取电路以一个双端口SRAM为中心，用二进制计数器产生存取地址、以十进制计数器产生欲存储的数据，读出的数据经过LED七段译码，送LED数码管显示-Data storage and reading circuit in a dual-port SRAM as the central access address generated using a binary counter to generate For decimal counter data stored, read out the data through LED seven-segment decoder, sending LED digital display Platform: |
Size: 434176 |
Author:william |
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Description: 可以实现二进制向十进制转换 输出时16进制的 可以用数码管显示-Binary to decimal conversion can be achieved when the 16 hex output LED display can be Platform: |
Size: 1024 |
Author:梁天尺 |
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