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[Embeded-SCM Develop] binary_to_bcd

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，bin转bcd-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, bin turn bcd
Platform: | Size: 2316 | Author: 秦拣俭 | Hits:

[Other resource] binary_to_bcd.tar

Description: binary_to_bcd is used for translating from binare to bcd.-binary_to_bcd is used for translating fro m binare to bcd.
Platform: | Size: 45262 | Author: 彭强 | Hits:

[Other resource] binary_to_bcd

Description: 关于进制数据转换的的，可以看看，里面有较完整的代码
Platform: | Size: 2320 | Author: yuhl | Hits:

[Embeded-SCM Develop] binary_to_bcd

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，bin转bcd-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, bin turn bcd
Platform: | Size: 2048 | Author: 秦拣俭 | Hits:

[VHDL-FPGA-Verilog] binary_to_bcd.tar

Description: binary_to_bcd is used for translating from binare to bcd.-binary_to_bcd is used for translating fro m binare to bcd.
Platform: | Size: 45056 | Author: | Hits:

[SCM] binary_to_bcd

Description: 关于进制数据转换的的，可以看看，里面有较完整的代码-On the M-ary data conversion, you can see, there are more complete code
Platform: | Size: 2048 | Author: yuhl | Hits:

[Windows Develop] binary_to_BCD

Description: 4位二进制码到8421BCD码的转换器。-4-bit binary code to BCD code converter.
Platform: | Size: 329728 | Author: lzj | Hits:

[Other] binary_to_bcd

Description: this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder-this is a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder
Platform: | Size: 1024 | Author: hassan | Hits:

[Other] binary_to_BCD

Description: 将二进制码转换成BCD码，在verilog环境下可以封装为译码器-BCD code into the binary code in verilog environment is encapsulated as decoder
Platform: | Size: 225280 | Author: dmt08 | Hits:

[VHDL-FPGA-Verilog] extension_pack_latest.tar

Description: This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code. Automatic count stop/start value generation functions. You enter a time duration and clock frequency and the value is automatically computed. Your choice of binary or LFSR number spaces. LFSR counters created by function call. clock generation procedures type and number conversion functions: synthesizable binary_to_BCD and BCD_to_binary functions synthesizable BCD_to_seven_segment display functions string value to std_logic_vector: "32" -> "0100000" Status
Platform: | Size: 1069056 | Author: Louis | Hits:

[VHDL-FPGA-Verilog] binary_to_BCD

Description: 本人编写的2进制转换为BCD码的verilog程序，绝对可用，已测试通过。-I write binary to BCD verilog program, absolutely free, have been tested.
Platform: | Size: 1024 | Author: 范志荣 | Hits:

[Embeded-SCM Develop] binary_to_bcd

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，bin转bcd-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, bin turn bcd
Platform: | Size: 2048 | Author: perce | Hits:

[Embeded-SCM Develop] binary_to_bcd

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，bin转bcd-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, bin turn bcd
Platform: | Size: 2048 | Author: alsosho | Hits:

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