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[VHDL-FPGA-Verilog] 32addjiafaqi

Description: 32位加法器组成原理课程设计，串行进位完成，希望对大家有帮助-32-bit adder composed of the principle of curriculum design, the serial binary completed, we hope to help
Platform: | Size: 36864 | Author: 常鹏程 | Hits:

[VHDL-FPGA-Verilog] multiplyingunit

Description: 其乘法器原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位-Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the left after the first and add if for 0, the left After the zero-sum in full, until the highest bit multiplicand
Platform: | Size: 137216 | Author: 张华 | Hits:

[VHDL-FPGA-Verilog] 8bitadder

Description: 串行8位加法器工程，已编译成功.标准代码VHDL语言-Serial 8-bit adder works have been compiled successfully
Platform: | Size: 303104 | Author: gaomeng | Hits:

[SCM] Case_Study_FA

Description: This document objective is to design a one bit full adder to be used as part of a serial adder.-This document objective is to design a one bit full adder to be used as part of a serial adder.
Platform: | Size: 398336 | Author: Bao | Hits:

[Software Engineering] serial-adder

Description: VHDL code for adding two hard-coded 8-bit binary numbers
Platform: | Size: 8192 | Author: harsha | Hits:

[Software Engineering] test_bench_8bitserialadder

Description: testbench for 8 bit serial binary adder
Platform: | Size: 6144 | Author: harsha | Hits:

[VHDL-FPGA-Verilog] 4BitSerialAdder

Description: Four Bit Serial Adder
Platform: | Size: 2048 | Author: George W | Hits:

[VHDL-FPGA-Verilog] assg-5-(serial-bit-adder)

Description: 4 bit adder using four full adder’s structural modeling style
Platform: | Size: 65536 | Author: milind | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 1.八进制计数器 2.八位右移寄存器 3.八位右移寄存器（并行输入串行输出） 4.半加 5.半加器 6.半减器 7.两数比较器 8.三数比较器 9.D触发器 10.T触发器 11.JK1触发器 12.JK触发器 13.三位全加器 14.SR触发器 15.T1触发器 16.三太门 17.有D触发器构成的6位2进制计数器 18.带同步置数的7进制减法计数器（6位右移寄存器） 19.二十四进制双向计数器 20.二选一 21.分频器 22.含同步清零的十进制加计数器 23.或门 24.7段译码器 25.8-3优先编码器 26.32位锁存器 27.八位左移寄存器 28.数据选择器4选1 29.两个三位二进制数全加器 -1 octal counter 2. Eight right register 3. Eight right register (parallel input serial output) 4 and a half plus 5 half adder 6. Half 7. Comparator compares the two numbers 8 Third number is 9.D trigger 10.T trigger 11.JK1 trigger 12.JK trigger 13. three full adder 14.SR trigger 15.T1 trigger 16. three too gate 17 with a D flip-flops 6-bit binary counter 18. 7 binary down counter with synchronous set number (6 right shift register) 19. twenty-four bidirectional binary counter 20. Alternative 21. divider 22. including synchronous clear plus zero decimal counter 23., or 24.7 Doors segment decoder 25.8-3 Priority Encoder 26.32 latch 27. eight left shift register 28. 4 election data selector 129. two three binary full adder implement
Platform: | Size: 4096 | Author: wanghao | Hits:

[VHDL-FPGA-Verilog] da2c

Description: VHDL硬件描述语言实现DA转化-In quurtus call half adder to achieve 16-bit serial adder
Platform: | Size: 3072 | Author: lemony | Hits:

[VHDL-FPGA-Verilog] SERIALADDER

Description: SERIAL ADDER 8-BIT-SERIAL ADDER 8-BIT
Platform: | Size: 6144 | Author: santosh | Hits:

[VHDL-FPGA-Verilog] Serial_Adder

Description: 注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加-Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder
Platform: | Size: 533504 | Author: | Hits:

[Embeded-SCM Develop] exp01_adc32

Description: 通过4位加法器实现32位加法器，使用串行进位的方式首先设计一个8位全加器，然后在8位全加器的基础上设计实现32位全加器(A 32 bit adder is implemented through a 4 bit adder. First, a 8 bit full adder is designed using serial carry. Then, a 32 bit full adder is designed on the basis of 8 bit full adder.)
Platform: | Size: 542720 | Author: Dramazoey_wong | Hits:

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