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[VHDL-FPGA-Verilogslice

Description: A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually internal to the CPU.For example,two 4-bit ALUs could be arranged side by side,with control lines between them,to form an 8-bit ALU.Asequencer executes a program to provide data and control signals.Slice construction conceptually proceeds in two phases.(1) detecting the slice, and (2)extracting the instructions for storage in the slice cache.Detection is done by propagating a dependance vector or DV as follows:Starting from the candidate load send its DV to the immediate preceding slicer entry.Entry checks the bit of the incoming DV .Because it is zero,it just propagates the DV as is to entry 8-A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually internal to the CPU.For example,two 4-bit ALUs could be arranged side by side,with control lines between them,to form an 8-bit ALU.Asequencer executes a program to provide data and control signals.Slice construction conceptually proceeds in two phases.(1) detecting the slice, and (2)extracting the instructions for storage in the slice cache.Detection is done by propagating a dependance vector or DV as follows:Starting from the candidate load send its DV to the immediate preceding slicer entry.Entry checks the bit of the incoming DV .Because it is zero,it just propagates the DV as is to entry 8
Platform: | Size: 1024 | Author: gopan | Hits:

[matlabprc5

Description: image bit plane slice and bit plane anding
Platform: | Size: 294912 | Author: rg007 | Hits:

[assembly language51MOVE

Description: 将片内50H~5FH及片外0010H~004FH单元清0;然后将片 内30H~3FH的数据移到片外0000H~000FH中;判断: 若(30H)≤15,则求其平方存到40H中,并将位00H置1 若(30H)=15, 则加15存到40H中,并位01H置1 若(30H)≥15, 则减15存到40H中,并位02H置1   -The on-chip and off-chip 50H ~ 5FH 0010H ~ 004FH unit cleared then slice The data 30H ~ 3FH moved to chip in 0000H ~ 000FH judgment: If (30H) ≤ 15, is seeking to keep its square 40H, and 00H and the bit is set to 1 If (30H) = 15, then add 15 deposit to 40H, and 01H and the bit is set to 1 If (30H) ≥ 15, then subtract 15 deposit to 40H, and 02H and bit set to 1
Platform: | Size: 1024 | Author: Allen | Hits:

[OtherUnivShiftReg

Description: 移位寄存器的bit slice,其中可以用其来构建其他多位寄存器-Universal Shift Register Bit Slice
Platform: | Size: 1024 | Author: 郑颖 | Hits:

[VHDL-FPGA-VerilogArray_slice_1Dx1D_of-bit-vector

Description: Array slice 1dx1D for individual access of element
Platform: | Size: 93184 | Author: mproject | Hits:

[Internet-Networkmain

Description: SOCKET编程本地通信 捕获本机网卡的IP包,对捕获的IP包进行解析。要求必须输出以下字段:版本号、总长度、标志位、片偏移、协议、源地址和目的地址。(SOCKET programming local communication Capture the IP packet of the local network card and parse the captured IP package. The following fields are required to be output: version number, total length, flag bit, slice offset, protocol, source address, and destination address.)
Platform: | Size: 2048 | Author: Fancyfxy | Hits:

[Linux-Unix7.滴答定时器实验

Description: Systick就是一个定时器而已,只是它放在了NVIC中,主要的目的是为了给操作系统提供一个硬件上的中断(号称滴答中断)。滴答中断?这里来简单地解释一下。操作系统进行运转的时候,也会有“心跳”。它会根据“心跳”的节拍来工作,把整个时间段分成很多小小的时间片,每个任务每次只能运行一个“时间片”的时间长度就得退出给别的任务运行,这样可以确保任何一个任务都不会霸占整个系统不放。或者把每个定时器周期的某个时间范围赐予特定的任务等,还有操作系统提供的各种定时功能,都与这个滴答定时器有关。因此,需要一个定时器来产生周期性的中断,而且最好还让用户程序不能随意访问它的寄存器,以维持操作系统“心跳”的节律。 只要不把它在SysTick控制及状态寄存器中的使能位清除,就永不停息。(Systick is just a timer, but it is put in NVIC. Its main purpose is to provide a hardware interrupt (known as a tick interrupt) to the operating system. Tick break? Here is a brief explanation. When the operating system is running, there will be a "heartbeat". It will work according to the beat of "heartbeat" and divide the whole time period into many small time slices. Each task can only run one time slice, so it has to quit to other tasks to run, so as to ensure that no task will occupy the whole system. Or give a certain time range of each timer cycle to a specific task, and various timing functions provided by the operating system are related to the tick timer. Therefore, a timer is needed to generate periodic interrupts, and it is better to keep the operating system "heartbeat" rhythm by preventing the user program from accessing its registers at will. As long as the enable bit in systick control and status register is not cleared, it will never stop.)
Platform: | Size: 1067008 | Author: 佛道 | Hits:

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