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[Other resource] P4_PPC_SDRAM_Reference_Design

Description: SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
Platform: | Size: 33819 | Author: 庞志勇 | Hits:

[VHDL-FPGA-Verilog] blockram

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 21504 | Author: 孙强 | Hits:

[Software Engineering] P4_PPC_SDRAM_Reference_Design

Description: SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM-SDRAM reference design: mainly include The following figure shows a high-level block diagram for this reference design followed by a briefdescription of each sub-section. The design consists of: PowerPC processor PLB-OPB bridge BlockRAM Memory Controller SDRAM Controller Two GPIO ports A UART Port External SDRAM
Platform: | Size: 33792 | Author: 庞志勇 | Hits:

[VHDL-FPGA-Verilog] BlockRAM

Description: xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
Platform: | Size: 2048 | Author: blackmew | Hits:

[VHDL-FPGA-Verilog] fifo_src

Description: verilog语言实现，利用BlockRAM实现FIFO。-Verilog language, the use of BlockRAM achieve FIFO.
Platform: | Size: 3072 | Author: blackmew | Hits:

[VHDL-FPGA-Verilog] shift_regeister

Description: 用blockram实现移位寄存器，开发语言为verilog hdl-Shift register with blockram achieve the development language for the verilog hdl
Platform: | Size: 148480 | Author: 郭淮 | Hits:

[VHDL-FPGA-Verilog] BlockRam

Description: xilinx FPGA BlockRam source.
Platform: | Size: 2048 | Author: zhanglingxiao | Hits:

[VHDL-FPGA-Verilog] BlockRam

Description: 块状ram使用实例，实现深度和宽度可调的FIFO，buffer。-The block ram instance, depth and width adjustable FIFO, buffer.
Platform: | Size: 2963456 | Author: zwl6600233 | Hits:

[VHDL-FPGA-Verilog] ramIPcore

Description: 基于quartusII的ram调用，利用FPGA自身的blockram创立ram的ip core-Based on the ram quartusII calls itself blockram created using FPGA ram' s ip core
Platform: | Size: 745472 | Author: yuyeluo | Hits:

[Com Port] ug480-ver1.5

Description: 利用实验板上的XADC资源，对芯片温度、内部电源进行定时采集和监控，并把信息存入blockram,可实现翻看，并有按键消抖模块-XADC resource use experimental board, the chip temperature, the internal power supply timing collection and monitoring, and put information into blockram, look can be achieved, and a key debounce module
Platform: | Size: 6645760 | Author: 梅兰竹菊 | Hits:

[VHDL-FPGA-Verilog] bram_shift_reg_w16x3072

Description: 使用 xilinx blockram 做连续shift 在图像处理中 做多行缓存很方便-Using blockram Xilinx as a continuous shift in the image processing to do more than the cache is convenient
Platform: | Size: 1024 | Author: huachaoge | Hits:

[Home Personal application] utosnet_latest.tar

Description: The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC. The framework is based on the Node-on-Chip architecture (link to paper coming). It works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access the PC (through uTosNet) and the other port exposed to access user-defined modules. This allows easy and generic storage of process variables. Currently two versions of uTosNet are supported: PC side USB converter chip UART FPGA PC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA-The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC. The framework is based on the Node-on-Chip architecture (link to paper coming). It works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access the PC (through uTosNet) and the other port exposed to access user-defined modules. This allows easy and generic storage of process variables. Currently two versions of uTosNet are supported: PC side USB converter chip UART FPGA PC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA
Platform: | Size: 7190528 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] pg058-blk-mem-gen

Description: blockram的手册，适合开发者使用是xilinx的(Blockram manual, suitable for developers to use, is Xilinx)
Platform: | Size: 1636352 | Author: CrazyICer | Hits:

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