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[VHDL-FPGA-Verilog] bluespec-h264_latest.tar

Description: h264 vhdl/verilog implementation on FPGA platform
Platform: | Size: 16850944 | Author: ravi | Hits:

[VHDL-FPGA-Verilog] bluespec-80211atransmitter_latest.tar

Description: This package implements a parameterized baseband hardware logic for an 802.11a Transmitter. This project has since been subsumed by the OFDM baseband project which can also be found on opencores.-This package implements a parameterized baseband hardware logic for an 802.11a Transmitter. This project has since been subsumed by the OFDM baseband project which can also be found on opencores.
Platform: | Size: 265216 | Author: chaitanya | Hits:

[VHDL-FPGA-Verilog] h264.tar

Description: h.264 bluespec system verilog source code
Platform: | Size: 1040384 | Author: datonglii | Hits:

[Communication-Mobile] ofdm.tar

Description: ofdm bluespec system verilog source code
Platform: | Size: 238592 | Author: datonglii | Hits:

[assembly language] bluespec-reedsolomon_latest.tar

Description: Reed Solomon decoder implemented in VHDL/Verilog. Includes ASM s
Platform: | Size: 33792 | Author: ahmed | Hits:

[VHDL-FPGA-Verilog] bluespec-h264_latest.tar

Description: H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
Platform: | Size: 16858112 | Author: YUKAI ZHANG | Hits:

[VHDL-FPGA-Verilog] hdlrecord

Description: Bluespec sample program and program for comparator. Cyclone 2 FPGA Real Time Clock program.
Platform: | Size: 360448 | Author: ad | Hits:

[Special Effects] bluespec-h264_latest.tar

Description: 基于xilinx FPGA的H.264视频标准的视频解码编程。-realtime H.264/AVC baseline decoder by xilinx fpga
Platform: | Size: 16858112 | Author: chenbq | Hits:

[Education soft system] Domain Specific Hardware Accelerators: Vector Processing Units

Description: This repository contains the source code for VLSI CAD Project, Domain Specific Hardware Accelerators, as apart of coursework in CS6230 : CAD for VLSI. Fall, 2020. What does this repo enclose? Overview The following components are implemented in Bluespec System Verilog: CPU RAM Bus Vector Processor CPU A minimal 2 stage pipelined inorder processor. Vector Processor A vector processor capable of: Vector Negation (int8, int16, int32, float32) Vector Minima (int8, int16, int32, float32)
Platform: | Size: 3301613 | Author: nalevihtkas | Hits:

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