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Description: MIPS 仿真器，能够实现汇编，反汇编和模拟运行。自己开发的，java课的大程，可能问题比较多，仅做参考，而且程序架构也设计地不是很好。但作为新手大程学习和简单的MIPS模拟还是没有问题的。
本 MIPS 模拟器支持的指令如下：
add,addi,sub,subi,and,andi,or,ori,nor,beq,bne,j,jr,jal,lw,lh,lb,sw,sh,sb, 其中所有的跳
转指令第三个操作数只能为一个行标签[不支持相对地址以及绝对地址]，标签可
以写在一行开头，以冒号结尾。
-MIPS emulator, be able to achieve a compilation of anti-compilation and simulation is running. Their own development, java classes big way, may be more questions, just make a reference, but also architecture design process is not very good. But as a new large study and easy way of MIPS simulation of the problem or not. The MIPS simulator supports the following commands: add, addi, sub, subi, and, andi, or, ori, nor, beq, bne, j, jr, jal, lw, lh, lb, sw, sh, sb, one of all of the Jump instruction operand can only be the third for a tag line [do not support the relative address and absolute address] can be written on the tag line at the beginning to the end of the colon.
Platform: |
Size: 1490944 |
Author: ly |
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Description: 暗黑1.09战网开源的程序。 -bnetd
Platform: |
Size: 1502208 |
Author: xuc |
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Description: this a muti cycle mips code that it can do mutiply,add,sub,xor,beq,bne,slt,sltu,ori,xori and... and it take address and data and then operate on them.-this is a muti cycle mips code that it can do mutiply,add,sub,xor,beq,bne,slt,sltu,ori,xori and... and it take address and data and then operate on them.
Platform: |
Size: 5120 |
Author: sajad |
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Description: mips single cycle
verilog code
for add,sub,bne,slt,lw,sw,xori instructions-mips single cycle
verilog code
for add,sub,bne,slt,lw,sw,xori instructions
Platform: |
Size: 8192 |
Author: nhan |
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Description: 32位多周期MIPS微处理器设计代码。具体功能：
运行下列的6类32条MIPS32指令。
算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。
逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。
移位指令：SLL、SLLV、SRL、SRLV、SRA。
条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。
无条件跳转指令：J、JR。
数据传送指令：LW、SW。
-Multi-cycle MIPS microprocessor design code
Platform: |
Size: 15360 |
Author: 姬一 |
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Description: 设计一个32位流水线MIPS微处理器，具体要求如下：
1. 至少运行下列MIPS32指令。
①算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。
②逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。
③移位指令：SLL、SLLV、SRL、SRLV、SRA。
④条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。
⑤无条件跳转指令：J、JR。
⑥数据传送指令：LW、SW。
⑦空指令：NOP。
2. 采用5级流水线技术，对数据冒险实现转发或阻塞功能。
3. 在XUP Virtex-II Pro开发系统中实现MIPS微处理器，要求CPU的运行速度大于25MHz。-Design a 32-bit pipelined MIPS microprocessor, the specific requirements are as follows: 1. At least run the following MIPS32 instruction. ① arithmetic instructions: ADD, ADDU, SUB, SUBU, ADDI, ADDIU. ② logical operation instructions: AND, OR, NOR, XOR, ANDI, ORI, XORI, SLT, SLTU, SLTI, SLTIU. ③ shift instruction: SLL, SLLV, SRL, SRLV, SRA. ④ conditional branch instruction: BEQ, BNE, BGEZ, BGTZ, BLEZ, BLTZ. ⑤ unconditional jump instruction: J, JR. ⑥ data transfer instruction: LW, SW. ⑦ dummy: NOP. (2) using five pipeline technology, adventure on the forwarding or blocking of data functions. 3 In the XUP Virtex-II Pro development system to achieve MIPS microprocessors, requires the CPU to run faster than 25MHz.
Platform: |
Size: 12288 |
Author: Peter |
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Description: Mips Simulator in c. Implemented operations =>
OPCODES {
ADDI=0x08, ANDI=0x0C, BEQ=0x04, BNE=0x05, EXT=0x00, J=0x02, JAL=0x03, LW=0x23, ORI=0x0D, SW=0x2B
}
FUNCT {
ADD=0x20, SUB=0x22, MULT=0x18, AND=0x24, OR=0x25, XOR=0x26,
NOR=0x27, SLT=0x2A, JR=0x08, SLL=0x00, SRL=0x02,
SRA=0x03, SYSCALL=0x0c, MFHI=0x10, MFLO=0x12
}
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Size: 1699840 |
Author: populoso |
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Description: 1、PC和寄存器组使用时钟触发。
2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。
3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。
4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。(1, PC and register groups are clocked.
2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit.
3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own.
4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)
Platform: |
Size: 6144 |
Author: Animal
|
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