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[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序 DL : 0: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Update : 2025-02-17 Size : 1kb Publisher : 夏社
[DSP program] FIR2 DL : 0: FIR. 该程序用线性缓冲区和间接寻址方法实现FIR滤波器-FIR. The process by linear buffer and indirect methods of addressing the achievement of FIR filter
Update : 2025-02-17 Size : 1kb Publisher : pu
[VHDL-FPGA-Verilog] fifo89 DL : 0: 先进先出FIFO缓冲器，8位字宽，9位字深，很简易的缓冲器。-FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
Update : 2025-02-17 Size : 263kb Publisher : gdfrg