Description: ecToDO Framework 是一个轻巧的,易于使用的基于PHP5的快速开发框架,旨在封装php开发过程中的一些通用流程,使开发者能够专注于功能的实现,以达到加速php应用程序的开发速度.它具有以下特点:
a.流程封装,采用MVC分层结构,易理解,易使用,易扩展
b.使用流行的smarty及pear,同时支持自主扩展
c.内置权限验证,支持自定义权限验证方式
d.方便的客户数据验证方式,自动生成客户端验证代码,并支持扩展
e.使用Factory方式包装model,自定义类库及第三方类库,轻松载入,轻松管理-ecToDO Framework is a lightweight, Based on the easy-to-use PHP5 framework for the rapid development, php Packaging to the process of developing some common procedures, so that developers can focus on the realization of functions, php to achieve accelerated application development speed. It has the following characteristics : a. Process Packaging, Using MVC hierarchical structure, easy to understand and easy to use, b. easy to expand the use of popular smarty and pear, while supporting the expansion c. built-in self test competence, Since the definition of competence to support authentication d. convenient customer data validation, automatic generation client authentication code, and support the expansion of the use of e. Factory methods of packaging model, a custom library, and third-part Platform: |
Size: 254598 |
Author:ck |
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Description: 现代先进微处理器有非常高的集成度和复杂度，又有寄存器堆、Cache等嵌入式部件，而且芯片管脚数相对较少，必须要有一定的自测试设计和其它的可测试性设计来简化测试代码，提高故障覆盖率。本文简要讨论NRS4000微处理器芯片的以边界扫描测试为主体，以自测试为补充的可测试性设计框架。着重介绍芯片的边界扫描设计和芯片中译码控制器PLA和微程序ＲＯＭ以及采用内嵌RAM结构的指令Cache和寄存器堆的内建自测试设计。仿真结果表明，这些可测试性设计大大缩短了测试代码的长度。-modern microprocessors have a very high degree of integration and complexity, there Register pile, Cache such as embedded components, but Chip few relatively small, There must be the self-test design and testing of other design code to simplify testing, fault coverage. This paper briefly discussed Key words microprocessor chip to the boundary-scan test as the mainstay, Since the test to add to the test design framework. Highlighting the boundary-scan chip design and chip decoder PLA and micro-controller procedures and the use of embedded ROM RA M structure of the instruction cache and register stack of built-in self-test design. The simulation results show that these tests can greatly shorten the design of the test code length. Platform: |
Size: 41303 |
Author:chengp |
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Description: ecToDO Framework 是一个轻巧的,易于使用的基于PHP5的快速开发框架,旨在封装php开发过程中的一些通用流程,使开发者能够专注于功能的实现,以达到加速php应用程序的开发速度.它具有以下特点:
a.流程封装,采用MVC分层结构,易理解,易使用,易扩展
b.使用流行的smarty及pear,同时支持自主扩展
c.内置权限验证,支持自定义权限验证方式
d.方便的客户数据验证方式,自动生成客户端验证代码,并支持扩展
e.使用Factory方式包装model,自定义类库及第三方类库,轻松载入,轻松管理-ecToDO Framework is a lightweight, Based on the easy-to-use PHP5 framework for the rapid development, php Packaging to the process of developing some common procedures, so that developers can focus on the realization of functions, php to achieve accelerated application development speed. It has the following characteristics : a. Process Packaging, Using MVC hierarchical structure, easy to understand and easy to use, b. easy to expand the use of popular smarty and pear, while supporting the expansion c. built-in self test competence, Since the definition of competence to support authentication d. convenient customer data validation, automatic generation client authentication code, and support the expansion of the use of e. Factory methods of packaging model, a custom library, and third-part Platform: |
Size: 253952 |
Author:ck |
Hits:
Description: 现代先进微处理器有非常高的集成度和复杂度，又有寄存器堆、Cache等嵌入式部件，而且芯片管脚数相对较少，必须要有一定的自测试设计和其它的可测试性设计来简化测试代码，提高故障覆盖率。本文简要讨论NRS4000微处理器芯片的以边界扫描测试为主体，以自测试为补充的可测试性设计框架。着重介绍芯片的边界扫描设计和芯片中译码控制器PLA和微程序ＲＯＭ以及采用内嵌RAM结构的指令Cache和寄存器堆的内建自测试设计。仿真结果表明，这些可测试性设计大大缩短了测试代码的长度。-modern microprocessors have a very high degree of integration and complexity, there Register pile, Cache such as embedded components, but Chip few relatively small, There must be the self-test design and testing of other design code to simplify testing, fault coverage. This paper briefly discussed Key words microprocessor chip to the boundary-scan test as the mainstay, Since the test to add to the test design framework. Highlighting the boundary-scan chip design and chip decoder PLA and micro-controller procedures and the use of embedded ROM RA M structure of the instruction cache and register stack of built-in self-test design. The simulation results show that these tests can greatly shorten the design of the test code length. Platform: |
Size: 40960 |
Author:chengp |
Hits:
Description: generation of wideband high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma–delta modulator chip. Via increasing the order of the one-bit bandpass sigma–delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma–delta modulator chip s production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.- generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma–delta modulator chip. Via increasing the order of the one-bit bandpass sigma–delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma–delta modulator chip s production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test. Platform: |
Size: 5120 |
Author:Nupur Naik |
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Description: BIST for RAMs using ASTRA:
Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this project, the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. In this project, it has been demonstrated that accumulator based compaction scheme Platform: |
Size: 243712 |
Author:sreekanth p |
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Description: In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also goes into detail in the design of the modules in the architecture and how the process works.
Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation.
- In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also goes into detail in the design of the modules in the architecture and how the process works.
Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation.
Platform: |
Size: 14336 |
Author:saravanan |
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Description: In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also goes into detail in the design of the modules in the architecture and how the process works.
Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation.
- In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also goes into detail in the design of the modules in the architecture and how the process works.
Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation.
Platform: |
Size: 3072 |
Author:saravanan |
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Description: PPT is about Built In self Test- is a mechanism that permits a machine to test itself.
PPT gives you good understanding about BIST. Platform: |
Size: 7020544 |
Author:rohit |
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Description: Built in self test to such that it generates non redundant inputs to tester using the concept of galois based primitive polynomial. Platform: |
Size: 7168 |
Author:Bela
|
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