Search - burst sdram

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[Other resource] sdram_control_burst DL : 0: 精简的sdram读写控制器例子，适用于数据采集系统，verilog，只支持burst方式的读写-streamlined read and write SDRAM controller example, applied to the data acquisition system, Verilog. only supports burst mode read and write
Update : 2008-10-13 Size : 150.51kb Publisher : 梁文锋
[VHDL-FPGA-Verilog] sdram_control_burst DL : 0: 精简的sdram读写控制器例子，适用于数据采集系统，verilog，只支持burst方式的读写-streamlined read and write SDRAM controller example, applied to the data acquisition system, Verilog. only supports burst mode read and write
Update : 2025-02-17 Size : 150kb Publisher : 梁文锋
[VHDL-FPGA-Verilog] burstpage DL : 0: SDRAM控制器在FPGA实现源代码，能实现burst传输-SDRAM controller in FPGA realization of the source code, can achieve burst transfer
Update : 2025-02-17 Size : 248kb Publisher : 弘历
[VHDL-FPGA-Verilog] rd1020 DL : 0: Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module.
Update : 2025-02-17 Size : 19kb Publisher : phwer01
[VHDL-FPGA-Verilog] source DL : 0: 本源码是基于VERILOG的SDRAM的开发与实现并能实现刷新，预充电，突发长度为8字节等功能已验证，可用-The source is based on the SDRAM VERILOG development and implementation and to achieve refresh, precharge, a burst length of 8 bytes and other functions have been verified, the available
Update : 2025-02-17 Size : 9kb Publisher : zhao
[VHDL-FPGA-Verilog] sdramcntl DL : 0: SDRAM Burst程序在XC3S系列FPGA有成功-SDRAM Burst Source code for XC3S series FPGA
Update : 2025-02-17 Size : 7kb Publisher : bingyu
[VHDL-FPGA-Verilog] sdram_sv DL : 0: sdram在quartus下的VerilogHDL描述，准确的是SystemVerilog，已调试成功，不过还没利用突发传输功能，内含modulesim的仿真文件。-sdram VerilogHDL under the quartus description is accurate SystemVerilog, has been commissioning successful, but not using burst transmission, the simulation file containing modulesim.
Update : 2025-02-17 Size : 4.72mb Publisher : Anthony
[Software Engineering] DDRSDRAM DL : 0: 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
Update : 2025-02-17 Size : 804kb Publisher : zhangjiefei
[Other] 0801sdram_burst8_better DL : 0: sdram burst=8控制模块,比较好的实现控制-sdram burst =8 control module，it is good for you to use it
Update : 2025-02-17 Size : 18kb Publisher : 樊满
[source in ebook] SDRAM_interface DL : 0: SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a refresh timer)
Update : 2025-02-17 Size : 2kb Publisher : bryan
[VHDL-FPGA-Verilog] sdram controller DL : 2: Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and the ability to randomly change column addresses on each clock cycle during a burst cycle. This reference design provides the user with a baseline SDRAM Controller design. The user may modify the design to meet specific design requirements. This document provides information on how this design operates and shows the user where changes can be made to support other functionality.
Update : 2025-02-17 Size : 8kb Publisher : Robuster
[VHDL-FPGA-Verilog] ddr_sdram DL : 0: 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造；支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较适合DDR入门使用(Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure; Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry)
Update : 2025-02-17 Size : 20kb Publisher : 唛侬