Search - cache Veril

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[VHDL-FPGA-Verilog] deinterlace DL : 0: Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
Update : 2025-02-17 Size : 97kb Publisher : cloud
[VHDL-FPGA-Verilog] cache DL : 0: 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
Update : 2025-02-17 Size : 4kb Publisher : MingCheng
[VHDL-FPGA-Verilog] lab1 DL : 0: xilinx sopc技术实例，请多多指教。一个很小的代码-xilinx sopc technical examples, please exhibitions. A very small code
Update : 2025-02-17 Size : 72kb Publisher : 庞志勇
[VHDL-FPGA-Verilog] mips1 DL : 0: Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
Update : 2025-02-17 Size : 18kb Publisher : Asparuh Grigorov
[VHDL-FPGA-Verilog] cameralink DL : 0: 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示出来-As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
Update : 2025-02-17 Size : 13kb Publisher : lilei