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[VHDL-FPGA-Verilogcalculator

Description: 用VHDL编写的计算器,能实现简单的加减乘除四则运算
Platform: | Size: 21504 | Author: huyanlong | Hits:

[Othercalculator

Description: 基于赛灵思的spartan-3e开发板的语音智能计算器的设计,开发语言verilog,开发软件ISE,可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解!-Development board based on Xilinx spartan-3e voice smart calculator design, development languages ​ ​ Verilog, developing software ISE, according to the ucf file to sort out the pin relationship. Application need to have some knowledge of the development board and fpga design!
Platform: | Size: 3531776 | Author: QIAO | Hits:

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