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[VHDL-FPGA-Verilog] cal_verilog DL : 0: 计算器芯片的verilog实现代码！时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success
Update : 2025-02-17 Size : 6kb Publisher : 徐哦俄
[VHDL-FPGA-Verilog] codeofvhdl2006 DL : 1: 【经典设计】VHDL源代码下载～～其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】 - [ Classics design ] the VHDL source code downloads ~ ~ classics the design to include: [ Vending machine ], [ electron clock ], [ traffic light traffic signal system ], [ step of 杩涚數 machine localization control system ], [ direct current machine speed control system ], [ calculator ], [ array LED display control system ] the basic numeral logical design includes: [ Latch ], [ multichannel selector ], [ 涓夋
Update : 2025-02-17 Size : 43kb Publisher : senkong
[VHDL-FPGA-Verilog] calculator DL : 0: 用VHDL编写的计算器，能实现简单的加减乘除四则运算
Update : 2025-02-17 Size : 21kb Publisher : huyanlong
[VHDL-FPGA-Verilog] alu181 DL : 0: alu运算器vhdl代码，介绍了16中运算方法，可用于cpu的设计中-alu calculator VHDL code, introduction of 16 in computing methods, can be used for the design of cpu
Update : 2025-02-17 Size : 1kb Publisher : 赵心
[VHDL-FPGA-Verilog] verilog DL : 0: 组成原理的大作业，写一个计算器，用verilog语言写的-The composition of the major principles of operation, write a calculator, using the language written in Verilog
Update : 2025-02-17 Size : 8.53mb Publisher : 陈江
[VHDL-FPGA-Verilog] shifter DL : 0: 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。-SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions. CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co
Update : 2025-02-17 Size : 126kb Publisher : 623902748
[VHDL-FPGA-Verilog] Ballastic_Calculator DL : 0: Ballastic Calculator Interface designe for Army TANK (Xilinx Verilog, Schematics)
Update : 2025-02-17 Size : 2.57mb Publisher : Tomahawk
[VHDL-FPGA-Verilog] VerilogHDL DL : 0: 讲解非常好的Verilog hdl 教材-Explain the very good teaching Verilog hdl
Update : 2025-02-17 Size : 3.98mb Publisher : wxd
[VHDL-FPGA-Verilog] calculator DL : 1: 课设一个，又臭又长，是一个用verilog编写的计算器，对应革新科技的某个sopc开发平台，键盘会扫描，七段二极管会译码且是并行输出，上传的是整个工程，在该开发平台上基本正常，主程序段编写的较为幼稚，希望大家多多扔玉。注：主程序段预计做八位计算器，后来因为实验平台只有六个数码管无奈之下后两位没接，主程序中的ac有问题，在开发平台上没效果，压缩包里的图是主程序在quartus下的仿真图，开发环境是quartus，不知应选哪项。最后：初次上传欢迎指正 -Set up a class, but also smell and long, is a calculator written using verilog, corresponding to a sopc innovative science and technology development platform, the keyboard scan, seven-segment LED will be parallel decode and output, upload the entire project, In the normal development platform, the main program segment written in a more naive, I hope Members can throw jade. Note: The main program segment is expected to make eight calculators, and later because the experimental platform is only six digits after the two did not desperation then, the main program of the ac problems did not result in the development of platforms, compressed bag of Figure is the main program under the simulation diagram in quartus, development environment is quartus, do not know which of the election. Last: initial upload please correct me
Update : 2025-02-17 Size : 10.31mb Publisher : raven
[VHDL-FPGA-Verilog] presentar DL : 0: Verilog code calculator, add, rest, multiply, and increment-Verilog code calculator, add, rest, multiply, and increment
Update : 2025-02-17 Size : 1kb Publisher : jaja12
[VHDL-FPGA-Verilog] method DL : 0: i need to refer and search for calculator verilog.hope i can find answer from it.
Update : 2025-02-17 Size : 47kb Publisher : Mei juan
[VHDL-FPGA-Verilog] verilog_calculator DL : 0: 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
Update : 2025-02-17 Size : 16kb Publisher : 刘涛
[VHDL-FPGA-Verilog] Calculator DL : 0: 基于Verilog开发的计算器，希望对大家有帮助！-Verilog-based development of the calculator, we want to help!
Update : 2025-02-17 Size : 1.88mb Publisher : sun pei
[VHDL-FPGA-Verilog] calculator_final DL : 0: 清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，音乐计算器，完成两个三位数的运算，有注释，很强大-Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !
Update : 2025-02-17 Size : 2.03mb Publisher : 薛芬
[VHDL-FPGA-Verilog] luan-van DL : 0: design calculator using verilog
Update : 2025-02-17 Size : 10kb Publisher : Nick
[VHDL-FPGA-Verilog] verilog-calculator DL : 0: 基于verilog的计算器，实现简单的加减乘的运算，并有退格键和清零键-verilog calculator
Update : 2025-02-17 Size : 721kb Publisher : fsr
[VHDL-FPGA-Verilog] calculator DL : 0: 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator realized by verilog,which could operate addition and subtraction process
Update : 2025-02-17 Size : 1.2mb Publisher : zhou
[Other] calculator DL : 0: 这是一个设计16位计算器，运用Verilog HDL语言编写，可以实现简单的加减法计算。并且可以在Xilinx91i上仿真。其中 top.v文件为目录，calculator.v为计算器设计，display.v为显示设计，divclk.v为分频设计，keypad.v为键盘设计，并且testkeypad.v为检测程序。-design a 16-bit calculator using the Spartan 3 FPGA on the Digilent circuit board, with an additional 20-key keypad.With all the detailed codes of each function.
Update : 2025-02-17 Size : 13kb Publisher : wangdage
[Other] calculator DL : 0: 基于赛灵思的spartan-3e开发板的语音智能计算器的设计，开发语言verilog，开发软件ISE，可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解！-Development board based on Xilinx spartan-3e voice smart calculator design, development languages Verilog, developing software ISE, according to the ucf file to sort out the pin relationship. Application need to have some knowledge of the development board and fpga design!
Update : 2025-02-17 Size : 3.37mb Publisher : QIAO
[Other Embeded program] calculator DL : 0: EDA设计源代码，verilog计算器设计-EDA design source code, verilog calculator design
Update : 2025-02-17 Size : 568kb Publisher : jerry

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